Week12 - Interconnect Capacitive Crosstalk& important for high impedance nodes Vx Cxy Cy Cxy Vy ∆ = ∆ but usually line y is driven with a

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Unformatted text preview: Interconnect: Capacitive Crosstalk & important for high impedance nodes Vx Cxy Cy Cxy Vy ∆ + = ∆ but usually line y is driven with a finite resistance R In the case rise/fall time of the interfering signal is important and you want slow rise/fall time So if maximum speed is not required, rise time and fall time can be increased to decrease the effect of cross-talk & higher rise/fall time & higher power consumption ( direct path ) Vx Cxy Cy X Y Cxy Cy X Y R tr = 5psec tr = 100psec tr = 200psec tr = 500psec>RC & time constant of the line Vy Dut to cros talk t (nsec ) Design techniques to reduce cross-talk 1. avoid floating nodes 2. separate high impedance nodes from full-swing signals 3. increase rise/fall time subject to timing constant and direct path power 4. use differential signaling in sensitive low-swing wiring network & cross-talk is common signal and will be rejected 5. do not allow high cap. between two signal wires ( layout technique : have the wires run on different metallization ) 6. provide shielding wire (GND,V DD ) between two signal lines Effect of cross-talk on performance Cross-talk affects the timing performance of the circuit and is not just unwanted coupling(noise) Example Exactly at the same time Worst case : signal at Y is in opposite phase with X and Y...
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This note was uploaded on 02/19/2012 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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Week12 - Interconnect Capacitive Crosstalk& important for high impedance nodes Vx Cxy Cy Cxy Vy ∆ = ∆ but usually line y is driven with a

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