week14 - Random Access Memory BL BL WL VDD You can...

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Random Access Memory BL You can read/write at comparable speed BL WL DD V Q Q Six transistor CMOS RAM Read Operation active word line BL BL , are precharged to DD V eq ckt : (Q = 1) BL BL WL DD V 0 = Q min DD V 2 . 1 × W Sense amp + Size of pass transistor has to be smaller than M1 to avoid read upset if the lines are precharged to better performance can be achieved + no read upset 2 DD V 1 > L W Pass L W NMOS Detect the difference between the two lines
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Write operation BL BL * and are set to different values * WL is activated This works identical to SR latch Cover powering the latch 8 . 1 > L W Pass L W PMOS 2 min × PMOS size imum Make it minimum Write time Æ dominated by tp of cross-coupled inverters Resistive SRAM Æ Replace PMOS with resistive loads * 4 trans instead of 6 * much smaller area since inter connection routing is easier + no need for n-well area of 3 2 * higher power consumption (in stand by) Resistors do not introduced slower cell as the precharge is done extrenally so make R as big as possible limt Æ area undoped poly as resistor T should provide current at least 2 ordered magnitude its cell taken cell A 15 10
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Dynamic RAM Resistor SRAM Æ resistor function is to provide current to compensate for leakage Æ we can omit the resistors and refresh the memory periodically Æ dynamic RAM refreshing Æ read the data then
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This note was uploaded on 02/19/2012 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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week14 - Random Access Memory BL BL WL VDD You can...

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