RFIC_Lecture_Note_No7_p93-p113 _Current & Voltage Referenà

RFIC_Lecture_Note_No7_p93-p113 _Current & Voltage Referenà

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ECE695F RFIC Prof. S. Mohammadi - 93 - Current & Voltage References why do we need voltage/current reference VCO DC V if this V DC varies as your power supply varies, you are in trouble Current Sources DD V ref I 2 D I neglecting finite output resistance ref D D I I I = = 1 2 since both transistors have same V GS what you need as a current reference is a current source 2 D I
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ECE695F RFIC Prof. S. Mohammadi - 94 - O R * I D does not change with changing V DS2 (infinite output resistance) DS V * I D does not change with temperature * There is always a gain error = 1 2 ref D I I 1) systematic gain error you can calculate it as due to ckt topology you have slight gain error 2) random gain error due to process variation transistor mismatch in V Th can do only statistical analysis * current sources always create a positive voltage drop (V IN ) we want to minimize V IN especially for low-bias application DD V IN V out V out I DD IN V V << sometimes we use more than one input terminal ( cascode current mirror ) to be able to operate at low V DD * A positive output voltage V out is needed such that ref D I I ~ min out V maximize range of output voltage const R which at 0
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ECE695F RFIC Prof. S. Mohammadi - 95 - Simple Current Mirror DD V IN I = 2 M 1 M G 2 D out I I = S out V often we say this is a diode connected transistor (while there is no diode when you short-ckt MOS drain to gate!) 2 2 2 ' 2 = L W k I V V D Th GS : ' k transconductance parameter µ ~ T as so I D is a function of temperature 2 2 2 2 1 1 1 1 2 1 ' 2 ' 2 + = + = L W k I V L W k I V V V D Th D Th GS identical transistors : operating in active mode with infinite output resistance! 2 1 2 1 2 1 ' ' = = = L W L W k k V V Th Th 2 1 D D I I = IN out I I = In practice if devices are not identical ( ) () IN out I L W L W I 1 2 = transistors can be ratioed to get gain < > 1 drawn eff S L not L as L ' L 5 . 0 18 . 0 13 . 0 technology
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ECE695F RFIC Prof. S. Mohammadi - 96 - So far we assumed drain current is independent of drain-source voltage In active region I D increases as V DS increases this is characterized by output resistance A V D I DS V early voltage 2 2 1 D D A O I I V R λ = = we know this parm as channel length modulation factor the good thing about MOS is that by increasing L (keeping W/L the same) you can improve output resistance 1 1 = = DS d D eff D O dV dX I L I r ( ) () + = A DS DS IN out V V V I L W L W I 1 2 1 2 1 systematic gain error of a simple current mirror A DS DS V V V 1 = ε
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ECE695F RFIC Prof. S. Mohammadi - 97 - The minimum output voltage needed to keep M 2 in saturation region () 2 min 2 2 ' 2 L W k I V V V V out out Th GS DS = > V out min depends on transistor geometary out I out DS V V 2 min out V if you reduce Th GS V V 2 you can still keep I out high enough by increasing ( ) 2 L W but there is a limit as you enter weak inversion instead of strong inversion transistor goes to subthreshold Th GS V V ~
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This note was uploaded on 02/19/2012 for the course ECE 695f taught by Professor Mohammadi during the Fall '09 term at Purdue.

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RFIC_Lecture_Note_No7_p93-p113 _Current & Voltage Referenà

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