lecture-07 - Code generation and local optimization...

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Code generation and local optimization Wednesday, October 12, 2011
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Generating assembly How do we convert from three-address code to assembly? Seems easy! But easy solutions may not be the best option What we will cover: Peephole optimizations Address mode selection “Local” common subexpression elimination “Local” register allocation More complex code generation Wednesday, October 12, 2011
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Naïve approach “Macro-expansion” Treat each 3AC instruction separately, generate code in isolation ADD A, B, C LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C MUL A, 4, B LD A, R1 MOV 4, R2 MUL R1, R2, R3 ST R3, B Wednesday, October 12, 2011
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Why is this bad? (II) MUL A, 4, B LD A, R1 MOV 4, R2 MUL R1, R2, R3 ST R3, B Wednesday, October 12, 2011
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Why is this bad? (II) MUL A, 4, B LD A, R1 MOV 4, R2 MUL R1, R2, R3 ST R3, B Too many instructions Should use a different instruction type Wednesday, October 12, 2011
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Why is this bad? (II) MUL A, 4, B LD A, R1 MOV 4, R2 MUL R1, R2, R3 ST R3, B Too many instructions Should use a different instruction type MUL A, 4, B LD A, R1 MULI R1, 4, R3 ST R3, B Wednesday, October 12, 2011
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Why is this bad? (II) ADD A, B, C LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C ADD A, B, C ADD C, A, E LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C LD C, R4 LD A, R5 ADD R4, R5, R6 ST R6, E Wednesday, October 12, 2011
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Why is this bad? (II) ADD A, B, C LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C ADD A, B, C ADD C, A, E LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C LD C, R4 LD A, R5 ADD R4, R5, R6 ST R6, E Redundant load of C Redundant load of A Uses a lot of registers Wednesday, October 12, 2011
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Why is this bad? (II) ADD A, B, C LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C ADD A, B, C ADD C, A, E LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C LD C, R4 LD A, R5 ADD R4, R5, R6 ST R6, E Redundant load of C Redundant load of A Uses a lot of registers Wednesday, October 12, 2011
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Why is this bad? (III) ADD A, B, C LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C ADD A, B, C ADD A, B, D LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C LD A, R4 LD B, R5 ADD R4, R5, R6 ST R6, D Wednesday, October 12, 2011
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Why is this bad? (III) ADD A, B, C LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C ADD A, B, C ADD A, B, D LD A, R1 LD B, R2 ADD R1, R2, R3 ST R3, C LD A, R4 LD B, R5 ADD R4, R5, R6 ST R6, D Wasting instructions recomputing A + B Wednesday, October 12, 2011
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How do we address this? Several techniques to improve performance of generated code Address mode selection to choose better instructions Peephole optimizations to remove redundant instructions Common subexpression elimination to remove redundant computation Register allocation to reduce number of registers used Wednesday, October 12, 2011
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Address mode selection Even a simple instruction may have a large set of possible address modes and combinations Dozens of potential combinations! + A B C
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This note was uploaded on 02/19/2012 for the course ECE 468 taught by Professor Test during the Fall '08 term at Purdue University-West Lafayette.

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lecture-07 - Code generation and local optimization...

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