{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}


QuantizeBinaryEncode - nmpmuuc Time Discretization...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 2
Background image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: nmpmuuc ' Time Discretization Discretization Quantization Amplitude Figure 1.4.8 Sampling and quantization of a sinusoidal signal. 1.4.4 Quantization of Sinusoidal Signals Figure 1.4.8 illustrates the sampling and quantization of an analog sinusoidal signal xa (t) = A cos Slot using a rectangular grid. Horizontal lines within the range of the quantizer indicate the allowed levels of quantization. Vertical lines indicate the sampling times. Thus, from the original analog signal xa (t) we obtain a discrete—time signal x(n) _= xa(nT) by sampling and a discrete-time, discrete-amplitude signal xq (n T) after quantization. In practice, the staircase signal xq (t) can be obtained by using a zero—order hold. This analysis is useful because sinusoids are used as test signals in A/D converters. “ If the sampling rate F5 satisfies the sampling theorem, quantization is the only error in the A/D conversion process. Thus we can evaluate the quantizatiOn error by quantizing the analog signal xa (t) instead of the discrete—time signal x(n) = xa (nT). Inspection of Fig. 1.4.8 indicates that the signal xa (t) is almost linear between quantization levels (see Fig. 14.9). The (a) (b) Figure 1.4.9 The quantization error eq (1‘) = xa (t) — xq(t). 6.3 Analog-to—Digital and Digital-to-Analog Converters 405 Output 5% = Q[x] Quantization levels \A 2A Two's—complement code words 01 1 010 001 000 1 1 1 Input 1 10 101 100 Decision levels l‘ Range R = FSR (Peak-to-peak range) Figure 6.3.3 Example of a midtread quantizer. There are various binary coding schemes, each with its advantages and disad- vantages. Table 6.1 illustrates some existing schemes for 3—bit binary coding. These number representation schemes are described in more detail in Section 9.4. The two’s—complement representation is used in most digital signal processors. Thus it is convenient to use the same system to represent digital signals because we can operate on them directly without any extra format conversion. In general, a (b + 1)-bit binary fraction of the form [80,81,132 - - - ,6], has the value ‘fiO‘ZO—i‘fll'2_1+,52'2—2+'”+,3b'Z—b if we use the two’s-complement representation. Note that ,80 is the most significant bit (MSB) and ,6b is the least significant bit (LSB). Although the binary code used to represent the quantization levels is important for the design of the A/D converter and the subsequent numerical computations, it does not have any effect in the per— formance of the quantization process. Thus in our subsequent discussions we ignore the process of coding when we analyze the performance of A/D converters. The only degradation introduced by an ideal converter is the quantization error, which can be reduced by increasing the number of bits. This error, which dominates the performance of practical A/D converters, is analyzed in the next section. Practical A/D converters differ from ideal converters in several ways. Various degradations are usually encountered in practice. Specifically, practical A/D convert— ers may have an offset errbr (the first transition may not occur at exactly +% LSB), TABLE 6.1 Commonly Used Bipolar Codes Decimal Fraction 7 Positive Negative Sign + Two’s Offset One’s Number Reference Reference Magnitude Complement Binary Complement +7 +§ —§ 0111 0111 1111 0111 +6 +§ +3 0110 0110 1110 0110 +5 +3 —3 0101 0101 1101 0101 +4 +§ +3 0100 0100 1100 0100 +3 +§ —§ 0011 0011 1011 0011 +2 +§ —§ 0010 0010 1010 0010 +1 +§ —% 0001 0001 1001 0001 0 0+ 0+ 0000 0000 1000 0000 0 0— 0+ 1000 (0000) (1000) 1111 —1 —§ +§ 1001 1111 0111 1110 +2 ~§ +§ 1010 1110 0110 1101 —3 —§ +3 1011 1101 0101 1100 —4 —3 +3 1100 1100 0100 1011 —5 —§ +§ 1101 1011 0011 1010 —6 —g +3 1110 1010 0010 1001 —7 —g +§ 1111 1001 0001 1000 —8 —§ +3 (100m @000) scale-factor (or gain) error (the difference between the values at which the first tr sition and the last transition occur is not equal to FS — ZLSB), and a linearity er (the differences between transition values are not all equal or uniformly changii If the differential linearity error is large enough, it is possible for one or more cc words to be missed. Performance data on commercially available A/D conver are specified in manufacturers’ data sheets. 6.33 v Analysis of Quantization Errors To determine the effects of quantization on the performance of an A/D conver we adopt a statistical approach. The dependence of the quantization error on characteristics of the input signal and the nonlinear nature of the quantizer mal deterministic analysis intractable, except in very simple cases. In the statistical approach, we assume that the quantization error is randon nature. We model this error as noise that is added to the original (unquantized) sig If the input analog signal is within the range of the quantizer, the quantization e1 ...
View Full Document

{[ snackBarMessage ]}