Correction de TP2 (1) - Correction de TP2 EX1: 1. lentit et...

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EX1: 1. l’entité et l’architecture de type flot de donnée d’une porte NXOR_3 : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity NXOR_3 is Port ( A : in std_logic; B : in std_logic; C : in std_logic; S : out std_logic); end NXOR_3; architecture Behavioral of NXOR_3 is begin s<= not(A xor B xor C); end Behavioral; 2. l’entité et l’architecture de type flot de donnée d’une porte AND_2 : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity AND_2 is Port ( A : in std_logic; B : in std_logic; S : out std_logic); end AND_2; architecture Behavioral of AND_2 is begin S<= A and B; end Behavioral; 3. l’entité et l’architecture de type flot de donnée d’une porte NAND_2 : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand_2 is Port ( A : in std_logic; B : in std_logic;
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This note was uploaded on 02/19/2012 for the course ELECTRONIC 1 taught by Professor Mannou during the Spring '12 term at Universidad de Negocios Isec.

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Correction de TP2 (1) - Correction de TP2 EX1: 1. lentit et...

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