hw4_solutions

# Hw4_solutions - Homework 4 Solutions ECE 152A Summer 2011 H.O#12 4.33 The cost of the circuit in Figure P4.2 is 11 gates and 30 inputs for a total

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Unformatted text preview: Homework 4 Solutions ECE 152A Summer 2011 H.O. #12 4.33. The cost of the circuit in Figure P4.2 is 11 gates and 30 inputs, for a total of 41. The functions implemented by the circuit can also be realized as f = x1 x2 x4 + x2 x3 x4 + x1 x3 x4 + x1 x4 g = x1 x2 x4 + x2 x3 x4 + x1 x3 x4 + x2 x4 + x3 x4 4.36. Using continuous assignment, the circuit in Figure 4.25b can be implemented using the code The ﬁrst three product terms in f and g are the same; therefore, they can be shared. Then, the cost of mo 24 i pr t b f 3 a ot , 2, x3, implementing f and g is 8 gates and dulenpuos, 4 or6 (tx1alxof 32. x4, x5, f); input x1, x2, x3, x4, x5; output f; 4.34. The cost of the circuit in Figure P4.3wir11ggat;es and 26 inputs, for a total of 37. The functions implemented is e , k by the circuit can also be realized as assign g = (x1 | x2 | x5); f = (x2 ↑ x4s) i↑ nx1 = (x2 ↑ x3 ) 4) (|x1 ↑ 3 2 ↑xx3;) ↑ (x2 ↑ x3 ) a s g ( k ↑ x3 & ∼x ↑ (∼x x & 4) a s g ( f x & ) | ↑ ( & ↑ x2 g = (x2 ↑ x4s) i↑ nx1=↑(g 2 ↑kx3 )(∼gx1 ∼k); ↑ x3 ) ↑ (x1 ↑ x1 ) The ﬁrst three NAND terms in f end mode the same; therefore, they can be shared. Then, the cost of implea g ar ule menting f and g is 7 gates and 20 inputs, for a total of 27. 4.35. Using gate level primitives, the circuit in Figure 4.25b can be implemented using the code 4.37. Using gate level primitives, the circuit in Figure 4.27c can be implemented using the code module prob4 35 (x1, x2, x3, x4, x5, f); input x1, x2, x3, x4, x5; module prob4 37 (x1, x2, x3, x4, x5, x6, x7, f); output f; input x1, x2, x3, x4, x5, x6, x7; output f; or (g, x1, x2, x5); not (notx3, x3); nand (a, x1, x1); not (notx4, x4); nand (b, x2, x3); and (a, x3, notx4); nand (c, a, b); and (b, notx3, x4); nand (d, x5, x5); o r ( k , a, b ) ; nand (e, x6, x6); and (c, g, k); nand (g, d, e); not (notg, g); nand (h, x4, g); not (notk, k); nand (j, x7, x7); and (d, notg, notk); nand (k, h, j); o r ( f , c, d ) ; nand (m, c, k); nand (f, m, m); endmodule endmodule 4.38. Usinsimoneistuous essiion ment, the circuit in Figure 4.27c can be implemented using the code 4.44. The g c pl t n expr ass gn is f = x1 x3 + x2 x3 (x1 + x4 ) module prob4 38 (x1, x2, x3, x4, x5, x6, x7, f); which can be implemented using phe cx1,ex2, x3, x4, x5, x6, x7; t ut od in output f; module a,rob4 44 (x1, x2, x3, x4, f); wire p b; input x1, x2, x3, x4; outpgn a ;= ∼(∼x1 & ∼(x2 & x3)); assi ut f assign b = ∼(∼(x4 & ∼(∼x5 & ∼x6)) & ∼x7); asssignff= (∼(∼(&4-9 3); | (x2 & x3 & (x1 | x4)); ∼b a sign = ∼x1 a & x ) ) endmodule endmodule 4-10 4.45. The simplest expression is f n (x1 + s 3 )wn + x l ows: 5.6. The associativity of the XOR operatio= can be xho(x1 as fo2 l+ x3 + x4 ) which can be implemented usx ⊕t(y ⊕ z ) = x ⊕ (y z + y z ) ing he code = 4 y z + y x , 3, x · + module probx(45 (x1, z )2+xx(y 4,zf); y z ) · x3 + x input =1, x2,y z , x4;y z + xy · z + xy z x output f; (x ⊕ y ) ⊕ z = (xy + xy ) ⊕ z not (notx1, x1); = ,x· ; not (notx2(x 2)y + xy )z + (xy + xy )z = , ); not (notx3xx·3y z + xy z + xy z + xy · z or (a, notx1, x3); The two SOP expressions are the same. or (b, x1, notx2, notx3, x4); and (f, a, b); 5.7. In the circuit of Figure 5.5b, we have: endmodule si = (xi ⊕ yi ) ⊕ ci = xi ⊕ yi ⊕ ci 4.46. The simplest expression is ci+1 = (xi ⊕ yi )ci + xi yi f = (x1= x3 )i(yi1+ xi y i+ x++ ix4 ) + (x x + x2 )ci 3 x yi which can be implemented using the code = xi yi ci + xi y i ci + xi yi 5.22. Using the approach explained in the solution to problem 5.21, the desired circuit can be built as follows: z5 z4 z3 z1 z2 FA z0 FA 2-bit adder Chapter 7 0 Result 57.1. Using the approach explained in the solutions to problems 5.21 and 5.22, the desired circuit can be built as .2 3 . follows: Clock z7 D z6 z5 z4 z3 z1 z2 z0 Qa HA FA FA s Qb s Qc 2-bit adder 7.2. The circuit in Figure 7.3 can be modiﬁed to implement an SR latch by connecting S to the Data input and S + R to the Load input. Thus the value of S is loaded into the latch whenever either S or R is asserted. 0 Care must be taken to ensure that the Data signal remains stable while the Load signal is asserted. 7 .7 . R Q 7 .3 . 2-bit adder R Qa S Qa Qb 1 Q 0/1 1/0 (no change) 1 0 0 1 0 1 1 0 0 Result R 1 Qb S 0 1 1 5-8 7 .8 . 7 .4 . 0 S J S Clk Clock QQ Q Q T K Q Q R 7.9. As the circuit in Figure P7.2 is drawn, it is not a useful ﬂip-ﬂop circuit, because setting C = 0 results in both of the circuit outputs being set to 0. Consider the slightly modiﬁed circuit shown below: 7-1 A D C ...
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## This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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