hw5_solutions

hw5_solutions - Homework 5 Solutions ECE 152A Summer 2011...

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Homework 5 Solutions ECE 152A Summer 2011 H.O. #13 6.20. Using the truth table in Figure 6.23a, the 4-to-2 binary encoder can be implemented as: module prob6 20 (W, Y); input [3:0] W; output reg [1:0] Y; always @(W) case (W) 4’b0001: Y = 2’b00; 4’b0010: Y = 2’b01; 4’b0100: Y = 2’b10; 4’b1000: Y = 2’b11; default: Y = 2’bxx; endcase 7 .1 7 . endmodule Up/down 7 .1 7 . 6.21. An 8-to-2 binary encoder can be implemented as: 0 Up/down QQ 0 Clock Q D D 1 Q 0 Q1 module prob6 21 (W, Y); input [7:0]Q ; W output reg [2:0] Y; D Q 1 Q2 Q 0 alwaysD (W) @Q DQ Q2 case (W) Q 1 1 8’b00000001: Y = 3’b000; Q Clock Q Q 8’b00000010: Y = 3’b001; 8’b00000100: Y = 3’b010; 7.18. The counting sequence is 000, 001, 010, 111. 8’b00001000: Y = 3’b011; 8’b00010000: Y = 3’b100; 8’b00100000: Y = 3’b101; 7.19. The circuit in Figure P7.4 is a master-slave JKbﬂip-00000: Y = er’bfr10; a problem sometimes called ones8’ 010 ﬂop. It suff 3 s 1 om catching. Consider the situation where the Q’b10put0i00l0:w, Clocb1= 1;, and J = K = 0. Now let Clock 8 out 00 s o Y = 3’ k 1 0 remain stable at 0 while J change from 0 to 1 efnd lt:eY ba3kbtxx0.; The master stage is now set to 1 and this a th n = c ’ o 7.18. Tale e ounltibe isecoreecteystr000, er01d010, 1he .slaveustage when thx clock changes to 1. 11 d a v h u c wil ng n qu r nc l i ansf 0 re , into tendcase e D QQ 0 0 1 endmodule 7.19. T ee circu t in F g i rn o7 4 is o mas s -seore JK ﬂi b ﬂ us. I s c f an e t m p pr t v em ge t e i gere c D ﬂi o ﬂo 7.20. Rhpeated iappliciatuoe Pf .DeMa rgant’erthlave m canp-e oped ttoufhersgfrohe a osioible-edsomritgmes d alled p-nesp cn tFigure 7.11 sndorthhensitutitie-edgeeD tthggQred tpiut ﬂs pow, Clock = 0, and J = K = 0. Now let Clock a ching. Coni i t e t e ega a von wh re ri e e ouﬂ p- i o l : i remain stable at 0 while J change from 0 to 1 and then back to 0. The master stage is now set to 1 and this value will be incorrectly transferred into the slave stage when the clock changes to 1. 6.22. The code in Figure P6.3 will instantiate latches on the outputs of the decoder because the if statement does not specify all possibilities in a combinational circuit. It can be ﬁxed by including the else clause 7.20. Repeated application of DeMorgan’s theorem can be used to change the positive-edge triggered D ﬂip-ﬂop in Figure 7.11 into the negative-edge D triggeredse iY[ﬂop: 0; el ﬂ p - k ] = after the if clause. Q Clock 6-7 Q Q Clock Q D D 7-8 7-8 7 .2 1 . module upcount12 (Resetn, Clock, Q); input Resetn, Clock; output reg [3:0] Q; always @(posedge Clock) if (!Resetn) Q <= 0; else if (Q == 11) Q <= 0; else Q <= Q + 1; endmodule 7 .3 1 . D Q 7.22. The longest delay in the circuit is the from the output of FF0 to the input of FF3 . This delay totals 5 ns. Thus the minimum period for which the circuit will operate reliably is Clock Tmin = 5 ns + tsu = 8 ns Q The maximum frequency is Fmax 7 .2 3 . Clock 1 0 D1 0 A1 0 Q1 0 7 .3 2 . = 1/Tmin A 125 MHz = module johnson8 (Resetn, Clock, Q); input Resetn, Clock; output reg [7:0] Q; reg [7:0] Q; always @(negedge Resetn, posedge Clock) if (!Resetn) Q <= 0; else Q <= {{Q[6:0]}, {∼Q[7]}}; endmodule Start Clock Reset 3-bit counter 7-9 f g 7.33. With non-blocking assignments, the result of the assignment f <= A[1] & A[0] is not seen by the successive assignments inside the for loop. Thus, f has an uninitialized value when the for loop is entered. Similarly, each for loop interation sees the unitialized value of f . The result of the code is the sequential circuit speciﬁed by f = f | A[n-1] A[n-2]. 7-12 K2 J1 = = w y 2 y0 w y 2 y0 K1 J0 = = w y0 w K0 = w The outputs are: z2 = y2 , z1 = y1 , and z0 = y0 . 8.25. Using the state-assigned table given in the solution for problem 8.23, the excitation table for T ﬂip-ﬂops is Flip-ﬂop inputs Present state y2 y1 y0 w=0 T2 T1 T0 T2 T1 T0 000 001 010 011 100 101 000 000 000 000 000 000 Outputs z2 z1 z0 w=1 001 011 001 111 001 101 000 001 010 011 100 101 The expressions for T inputs of the ﬂip-ﬂops are T2 = T1 = w y 1 y0 + w y 2 y0 w y 2 y0 T0 = w The outputs are: z2 = y2 , z1 = y1 , and z0 = y0 . 8.26. The state diagram is 8-15 Present Next state state w=0 w=1 A B C D E F G H H A B C D E F G Count C D E F G H A B 0 1 2 3 4 5 6 7 The state-assigned table is Present state y2 y1 y0 A B C D E F G H 000 001 010 011 100 101 110 111 Next state w=0 w=1 Y2 Y1 Y0 Y2 Y1 Y0 111 000 001 010 011 100 101 110 010 011 100 101 110 111 000 001 Output z2 z1 z0 000 001 010 011 100 101 110 111 The next-state expressions (inputs to D ﬂip-ﬂops) are D2 D1 = Y2 = Y1 = w y 2 y1 + w y 2 y1 + w y 2 y 1 + w y 2 y0 + y 2 y 1 y 0 w = w y 1 + y 1 y 0 + w y 1 y0 D0 = Y0 = y 0 w + y0 w The outputs are: z2 = y2 , z1 = y1 , and z0 = y0 . 8-16 ...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online