hw6_solutions

hw6_solutions - 7 .3 4 . r0 r1 r2 Homework 6 Solutions D Q...

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Unformatted text preview: 7 .3 4 . r0 r1 r2 Homework 6 Solutions D Q D Q Q D Q Q Q L Clock The counting sequence is: 001, 110, 011, 111, 101, 100, 010, 001 7 .3 . C5haptrer 8 r1 0 r2 8.1. The expressions for the inputs of the flip-flops are D Q Q D D2 D1 Q D = Y2 = w y2 + y 1 y 2 = Y1 = w ⊕ y1 ⊕ y2 Q The output equation is L Clock Q Q z = y 1 y2 The counting sequence is: 001, 101, 111, 110, 011, 100, 010, 001 8.2. The excitation table for JK flip-flops is 7 .3 6 . r0 r1 Present state y2 y1 D r2 Flip-flop inputs w=0 J2 K2 J1 K1 1d 0d d0 d0 0d d0 1d d1 00 01 10 Q 11 Q Output w=1 J2 K2 z J1 K1 1d 1d DQ 0d d1 d1 0d Q d1 d0 0 0 0 1 L The expressions for the inputs of the flip-flops are Clock J2 = The counting sequence is: 001, 100, 000, 000, ... K2 = J1 = y1 = J1 K1 The output equation is w w y2 + w y 2 7z 13 y1 y2 -= 8.3. A possible state table is Next state Output z Present state w=0 w=1 w=0 w=1 A B C D E F A E E E F A B C D D B B 0 0 0 0 0 0 0 0 0 1 0 1 8-1 D Q Q ECE 152A Summer 2011 H.O. #18 8.9. To compare individual bits, let k = w1 ⊕ w2 . Then, a suitable state table is Next state Output z Present state k=0 k=1 k=0 k=1 A B C D B C D D A A A A 0 0 0 1 0 0 0 0 The state-assigned table is 8.11. A possible minimum state table for a Moore-type FSM is Present Next State Output state k = 0 Nek t=tate k = 0 k = 1 x s1 Present Output y2 y1 z z statoblY2 Y1 .=20is2 Yw = 1 e emw 1 Y 1 z 8.13. Verilog code for the solution given in pr 8 00 01 00 0 0 01 A 1 ; B 00 C 0 0 0 module prob8 13 (Clock, Resetn, w, p)0 B D 00 E 0 0 0 11 input Clock, Resetn, w; 10 11 C 11 E 00 D 1 0 0 output p; D F G 0 reg [3:1] y, Y; E F F 0 01 The nextpstrae aetd r ut3:ut] expres’sions ,aB = 3’b0A , C = 3’b010, D = 3’b011, E = 3’b100, F = 3’b101; - a at m n e o [ p 1 A = 3 b000 Fre A 0 G A A 1 // Define the next state combinationa2 circuit k y1 + k y2 Yl = always @(w, y) Y1 = k y1 + k y2 case (y) z = k y 1 y2 A: if (w) Y = C; else Y = B; B: if (w) Y = E; else Y = D; C: if (w) Y = D; else Y = E; D: if (w) Y = F; 8.12. A minimum state telbee is shown below. We assume that the 3-bit patterns do not overlap. a sl Y = A; E: if (w) Y = A; else Y = F; Next state F: if (w) Y = C; Present Output else Y = B; state p w=0 w=1 default: Y = 3’bxxx; A B C 0 endcase B D E 0 E D 0 // Define the sequential block C D A F 0 always @(negedge Resetn, posedge Clock) F A 0 if (Resetn == 0) y <= A; E F B C 1 else y <= Y; // Define output assign p = (y == F); endmodule 8.14. The timing diagram is 8-6 Clock a b y, y 2 SMealy SumMoore 8-8 8-9 The output is given by z = y4 . 8.16. The state-assignment given in problem 8.15 can be used, except that the state variable y 1 should be complemented. Thus, the state assignment will be y4 y3 y2 y1 = 0000, 0011, 0101, and 1001, for the states A, B , C , and D, respectively. The circuit derived in problem 8.15 can be used, except that the signal for the state variable y1 should be taken from the Q output of flip-flop 1, rather than from its Q output. 8.17. The partitioning process gives P1 = (AB C DE F G) P2 P3 = (AB D)(C E F G) = (AB D)(C E G)(F ) P4 = (AB D)(C E G)(F ) 8-10 The minimum state table is Next state Output z Present state w=0 w=1 w=0 w=1 A C F A F C C C A 0 0 0 0 1 1 8.18. The partitioning process gives 8.33. The Verilog code based on the style of code in Figure 8.34 is P1 = (AB C DE F G) module prob8 33 (Clock, Reset= D,(ADG)(B C E F ) P2 n, N, z); input Clock, Resetn, D,P = (AG)(D)(B )(C E )(F ) N; 3 output z; P4 = (A)(G)(D)(B )(C E )(F ) reg [2:1] y; The minimiwide ta1e0] ble is ze r s [ t : ta K; parameter [2:1] S1 = 2’b00, S2 = 2’b01, S3 = 2’b10; assign K = {D, N}; // Define the sequential block Next state Output z always @(negedgePresenn, posedge Clock) Reset t t te if (Resetn == 0) sya<= S1w = 0 w = 1 w = 0 w = 1 ; else A B C 0 0 case (y) B 0 1 S1: if (K == 2’b00) y D = S1; − < C F C 0 1 else if (K == 2’b01) y <= S3; D B G 0 0 else if (K == 2’b10) y <= S2; F D 0 1 else y <= 2’bxx; C G F − 0 0 S2: if (K == 2’b00) y <= S2; else if (K == 2’b01) y <= S1; else if (K == 2’b10) y <= S3; else y <= 2’bxx; 8.19. An implementation fSr : he (Ko==e2type ) Sy <n Figures 8.5.7 and 8.5.6 is given in the solution for problem o 3 t if M or - ’b00 F M i= S3; 8.8. The Mealy-type FSM lise Ffgure 8.58b01)escribedS2; the form of a state table as e n i i (K == 2’ is d y <= in else if (K == 2’b10) y <= S1; else y <= 2’bxx; Output z defaPre:sent <= 2’bxxNext state ult y ; endcase state DN=00 01 10 11 00 01 10 11 // Define output S1 S1 S3 S2 − 0 0 0 1 assign z = ((y == S2) & ((KS2 2’S1 1) | (K == 2’b10))) |1((y =1 S3) & (K == 2’b10)); == b0 S3 − =− S2 0 S3 S3 S2 S1 − 0 0 1 − endmodule 8-11 8-22 ...
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This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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