hw7_solutions

hw7_solutions - Homework 7 Solutions ECE 152A Summer 2011...

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Unformatted text preview: Homework 7 Solutions ECE 152A Summer 2011 H.O. #20 // Define the sequential block always @(negedge Resetn, posedge Clock) if (Resetn == 0) y <= A; else y <= Y; endmodule 8.5. A minimal state table is Next State w=0 w=1 Present state A B C D E F A E D A A E Output z B C C F F C 0 0 0 1 0 1 8.6. An initial attempt at deriving a state table may be Next state Output z Present state w=0 w=1 w=0 w=1 A B C D E A D D A D B C C E C 0 0 1 0 0 0 0 0 1 0 States B and E are equivalent; hence the minimal state table is Next state Output z Present state w=0 w=1 w=0 w=1 A B C D A D D A B C C B 0 0 1 0 0 0 0 1 8-3 8.8. For Figure 8.55 have (using straightforward state assignment): Next state Present state y4 y3 y2 y1 S1 S2 S3 S4 S5 S6 S7 S8 S9 DN=00 01 10 Output 11 z Y4 Y3 Y2 Y1 0000 0001 0010 0011 0100 0101 0110 0111 1000 0000 0001 0010 0000 0010 0101 0000 0000 0010 0010 0011 0101 − − 0111 − − − 0001 0100 0110 − − 1000 − − − − − − − − − − − − 0 0 0 1 1 0 1 1 1 The next-state and output expressions are Y4 = D y3 Y3 Y2 = = D y1 + D y2 + N y2 + D y3 y 2 y1 N y 2 + y3 y 1 + N y 3 y2 y 1 Y1 z = = N y2 + D y 2 y 1 + D y 2 y1 y 4 + y1 y2 + y 1 y3 Using the same approach for Figure 8.56 gives Next state Present state y3 y2 y1 S1 S2 S3 S4 S5 DN=00 01 10 11 z Y3 Y2 Y1 000 001 010 011 100 000 001 010 000 010 010 011 001 − − Output 001 100 011 − − − − − − − 0 0 0 1 1 The next-state and output expressions are: Y3 = D y 2 y1 Y2 Y1 = y3 + N y2 y 1 + N y 2 = D y 2 y1 + N y2 y 1 + D y 3 y 1 z = y 3 + y2 y1 These expressions define a circuit that has considerably lower cost that the circuit resulting from Figure 8 .5 5 . 8-5 8.15. The state table corresponding to Figure P8.1 is Next state Present state w=0 w=1 Output z A B C D C B D C D A A B 0 0 0 1 Using one-hot encoding, the state-assigned table is Next state Present state y4 y3 y2 y1 The minimum state table is w=1 Output Y4 Y3 Y2 Y1 Y4 Y3 Y2 Y1 z 0001 0010 0100 1000 A B C D w=0 0100 0010 1000 0100 1000 0001 0001 0010 0 0 0 1 The next-state expressions are se Ou Present D Next Ytat= w y + wytput z 4= 4 3 1 state w = 0 Y w = 1 (yw + y0 ) w = 1 =w = D3 = 3 1 4 A D2 A 0 = Y2 C w y2 +0wy4 = C D F= Y C w(y + y ) 0 1 1 1= 2 1 F C A 0 1 The output is given by z = y4 . 8.18. The partitioning process gives 8.16. The state-assignment given in problem 8.15 can be used, except that the state variable y 1 should be complemented. Thus, the state assignmePt wi= be(y4B3C2 yE= G000, 0011, 0101, and 1001, for the states A, B , n1 ll A y y D1 F 0 ) C , and D, respectively. The circuit derived in problem 8.15 can be used, except that the signal for the state P2 = (ADG)(B C E F ) variable y1 should be taken from the Q output of flip-flop 1, rather than from its Q output. P3 = (AG)(D)(B )(C E )(F ) P4 8.17. The partitioning process gives The minimized state table is = (A)(G)(D)(B )(C E )(F ) P1 = (AB C DE F G) P2 P3 = (AB D)(C E F G) = (AB D)(C E G)(F ) Ne ( stat D Ou p = xt ABe )(C E G)(Ft) ut z Present P4 state w=0 A B C D F G B D F B C F w=1 w=0 w=1 0 0 0 0 0 0 C 8-10 − C G D − 0 1 1 0 1 0 8.19. An implementation for the Moore-type FSM in Figures 8.5.7 and 8.5.6 is given in the solution for problem 8.8. The Mealy-type FSM in Figure 8.58 is described in the form of a state table as Present state S1 S2 S3 Next state Output z DN=00 01 10 11 00 01 10 11 S1 S2 S3 S3 S1 S2 S2 S3 S1 − − − 0 0 0 0 1 0 0 1 1 1 − − 8-11 8.27. From the state-assigned table given in the solution to problem 8.26, the excitation table for JK flip-flops is Flip-flop inputs Present state y2 y1 y0 w=0 J2 K2 w=1 J1 K1 J0 K0 J2 K2 J1 K1 J0 K0 1d 1d d1 d1 1d 00 1d dz 1 d1 0 0 0 0d d0 0d d0 Output 0d 01 d 0 0 1 z 0 dz d0 0 0 1 1 0 1 0t 0 1d 1d 0d The state-assigned 0able is 1 d 001 0d 0d d1 0d 010 0d d1 1d 1d 011 0d d 0 Next 1 tate ds 1d Present 100 d1 1d 1d d0 state d 0 DN=0 0 0d 01 1 10 d 011 101 d 11 0 y2 y1 d 0 d 1 1 Y2 Y1 Y2 Y1d Y2 Y1 d Y2 Y1 1 111 d0 d0 d1 d1 00 00 10 01 − 01 01 00 10 − The expressions for J a10 K inputs to the th0ee flip-00 ps are− nd r1 flo 10 = = J2 The next-state and output expressions are K2 y1 w + y 1 y 0 w J2 Outputs z2 z1 z0 000 001 010 011 100 11 01 1 z110 111 − − − J = w+ N =1 Dy1 + Dyy 0 + N y 2 y 1 2 K1 N y +1Dy N + Dy y Y1 = = 2 J 1 21 J =w z = 0 D y1 + D y2 + N y1 K0 = J0 Y2 In thos cpues che:oz2n= ty2 , Mealyymodel results 0n a simpler circuit. The i ut as t , ar o si g he z1 = 1 , and z0 = y i . 8.20. Usem the thate-assi. ned natble stiventanlthis solution to problem 8.26, the excitation table for T flip-flops is 8.28. Fro w as st e clockgThe t h e g ate ib e e Present Present Next Output oa e statFlip-flstptinputs 1 z0 e z state y2 y1 y0 000 001 010 011 100 101 110 111 w=0 A TBT1 T0 2 C 11 1 D 01 0 011 001 111 001 011 Present 001 state y1 y0 The expressions for T inputs of the flip-flops are 00 T1 0 = 2 T0 1 = 1 T1 1 = 0 The state-assigned table is w = 1 Outputs B 00 z z z 210 T0 C T2 T11 0 D 010 1 0 000 A 010 1 1 001 110 010 110 011 010 100 010 101 110 110 Next 1Output 111 10 state Y1 Y0 z1 z0 10 00 y0 y 0 w + y10 11 1w 11 w + y0 0 1 0 11 w0 The nexp-stts te e:xz2e= iy2 ,szare y1 , and z0 = y0 .8-17 out t u aar e pr ss on 1 = Y1 8.29. The next-state and output expressions are = y1 Y2 = y1 ⊕ y2 D1 = Y1 D2 = Y2 = w(y 1 + y 2 ) z = y1 y 2 8-12 = w(y1 + y2 ) The corresponding state-assigned table is Next state Present state y2 y1 w=0 w=1 Y2 Y1 Y2 Y1 00 01 10 11 00 00 00 00 10 11 11 01 Present state w=0 w=1 z A B C D A A A A C D D B 0 1 0 0 Output z 0 1 0 0 This leads to the state table Next state Output The circuit produces z = 1 whenever the input sequence on w comprises a 0 followed by an even number of 1s. ...
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This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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