hw9_soln - B&V 7.24 The longest delay in the circuit is...

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Homework 9 Solutions ECE 0132 November 17, 2005 Problem 1 The circuit acts as a negative-edge-triggered JK flip-flop, in which J = A , K = B , Clock = C , Q = D , ¯ Q = E . Figure 1: Problem 2 (7.15): 4-bit shifter. 1
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Problem 2 Figure 2: Problem 2 (7.15): 4-bit synchronous counter with parallel load. 2
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Figure 3: Problem 2 (7.15): 3-bit asynchronous up/down counter. 3
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Figure 4: Problem 2 (7.15): 3-bit synchronous up/down counter. 4
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Problem 3 Figure 5: Problem 3 (7.17): 3-bit up/down counter using D flip flops. The circuit in Figure P7.4 is a master-slave JK flip-flop. It suffers from a problem sometimes called ones-catching . Consider the situation where the Q output is low, Clock = 0, and J = K = 0. Now let Clock remain stable at 0 while J change from 0 to 1 and then back to 0. The master stage is now set to 1 and this value will be incorrectly transferred into the slave stage when the clock changes to 1.
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Unformatted text preview: B&V 7.24 The longest delay in the circuit is the delay from the output of FF to the input of FF 3 . This delay totals 5 ns. Thus the minimum period for which the circuit will operate reliably is T min = t d + t su + t h = 5 + 3 + 1 = 9 ns. (1) The maximum frequency is F max = 1 T min = 111 MHz. (2) Problem 4 B&V 8.1 The expressions for the inputs of the flip-flops are D 2 = Y 2 = ¯ wy 2 + ¯ y 1 ¯ y 2 (3) D 1 = Y 1 = w XOR y 1 XOR y 2 (4) 5 B&V 8.2 The expressions for the inputs of the flip-flops are J 2 = ¯ y 1 (5) K 2 = w (6) J 1 = ¯ wy 2 + w ¯ y 2 (7) K 1 = J 1 (8) The output equation is z = y 1 y 2 (9) 6 B&V 8.3 Figure 6: Problem 4 (8.3): Possible state table for problem 8.3. Figure 7: Problem 4 (8.3): Possible state diagram for problem 8.3. 7...
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This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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hw9_soln - B&V 7.24 The longest delay in the circuit is...

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