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L4 - Propagation Delay Circuit Timing Adder Design ECE 152A...

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1 Propagation Delay, Circuit Timing & Adder Design ECE 152A – Fall 2006 October 12, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis 2.9.3 Functional Simulation 2.9.4 Summary 3 Implementation Technology 3.3.1 Speed of Logic Circuits 3.5 Standard Chips 3.5.1 7400-Series Standard Chips
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2 October 12, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment Brown and Vranesic (cont) 5 Number Representation and Arithmetic Circuits 5.1 Positional Number Representation 5.1.1 Unsigned Numbers 5.1.2 Conversion Between Decimal and Binary Systems 5.1.3 Octal and Hexadecimal Representations 5.2 Addition of Unsigned Numbers 5.2.1 Decomposed Full-Adder 5.2.2 Ripple-Carry Adder 5.2.3 Design Example October 12, 2006 ECE 152A - Digital Design Principles 4 Reading Assignment Roth 1 Introduction Number Systems and Conversion 1.2 Number Systems and Conversion 1.3 Binary Arithmetic 8 Combinational Circuit Design and Simulation Using Gates 8.3 Gate Delays and Timing Diagrams
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3 October 12, 2006 ECE 152A - Digital Design Principles 5 Propagation Delay When gate inputs change, outputs don’t change instantaneously This delay is known as “gate” or “propagation” delay PLH PHL t t = = 2 1 ε ε October 12, 2006 ECE 152A - Digital Design Principles 6 Propagation Delay ε 1 is the propagation delay from input going high to output going low (inverting logic) t PHL ε 2 is the propagation delay from input going low to output going high (inverting logic) t PLH Terminology ( t PHL and t PLH ) always refers to the transition on the output (whether circuit is inverting or not)
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