{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

L5 - Combinational Logic Design with Verilog ECE 152A Fall...

Info icon This preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Combinational Logic Design with Verilog ECE 152A – Fall 2006 October 17, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.10 Introduction to Verilog 2.10.1 Structural Specification of Logic Circuits 2.10.2 Behavioral Specification of Logic Circuits 2.10.3 How Not to Write Verilog Code
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 October 17, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment Brown and Vranesic (cont) 4 Optimized Implementation of Logic Functions 4.12 CAD Tools 4.12.1 Logic Synthesis and Optimization 4.12.2 Physical Design 4.12.3 Timing Simulation 4.12.4 Summary of Design Flow 4.12.5 Examples of Circuits Synthesized from Verilog Code October 17, 2006 ECE 152A - Digital Design Principles 4 Design Entry In previous examples, design entry is schematic based TTL implementation using standard, discrete integrated circuits PLD implementation using library of primitive elements Code based design entry uses a hardware description language (HDL) for design entry Code is synthesized and implemented on a PLD
Image of page 2
3 October 17, 2006 ECE 152A - Digital Design Principles 5 Verilog Design Structural Verilog Looks like the gate level implementation Specify gates and interconnection Text form of schematic Referred to as “netlist” Allows for “bottom – up” design Begin with primitives, instantiate in larger blocks October 17, 2006 ECE 152A - Digital Design Principles 6 Verilog Design RTL (Register Transfer Level) Verilog Allows for “top – down” design No gate structure or interconnection specified Synthesizable code (by definition) Emphasis on synthesis, not simulation vs. high level behavioral code and test benches No timing specified in code No initialization specified in code Timing, stimulus, initialization, etc. generated in testbench (later)
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
4 October 17, 2006 ECE 152A - Digital Design Principles 7 Half Adder - Structural Verilog Design Recall Half Adder description from schematic based design example Operation Truth table Circuit
Image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern