L5 - 1 Combinational Logic Design with Verilog ECE 152A...

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Unformatted text preview: 1 Combinational Logic Design with Verilog ECE 152A Fall 2006 October 17, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.10 Introduction to Verilog 2.10.1 Structural Specification of Logic Circuits 2.10.2 Behavioral Specification of Logic Circuits 2.10.3 How Not to Write Verilog Code 2 October 17, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment Brown and Vranesic (cont) 4 Optimized Implementation of Logic Functions 4.12 CAD Tools 4.12.1 Logic Synthesis and Optimization 4.12.2 Physical Design 4.12.3 Timing Simulation 4.12.4 Summary of Design Flow 4.12.5 Examples of Circuits Synthesized from Verilog Code October 17, 2006 ECE 152A - Digital Design Principles 4 Design Entry In previous examples, design entry is schematic based TTL implementation using standard, discrete integrated circuits PLD implementation using library of primitive elements Code based design entry uses a hardware description language (HDL) for design entry Code is synthesized and implemented on a PLD 3 October 17, 2006 ECE 152A - Digital Design Principles 5 Verilog Design Structural Verilog Looks like the gate level implementation Specify gates and interconnection Text form of schematic Referred to as netlist Allows for bottom up design Begin with primitives, instantiate in larger blocks October 17, 2006 ECE 152A - Digital Design Principles 6 Verilog Design RTL (Register Transfer Level) Verilog Allows for top down design No gate structure or interconnection specified Synthesizable code (by definition) Emphasis on synthesis, not simulation vs. high level behavioral code and test benches No timing specified in code No initialization specified in code Timing, stimulus, initialization, etc. generated in testbench (later) 4 October 17, 2006 ECE 152A - Digital Design Principles 7 Half Adder - Structural Verilog Design Recall Half Adder description from schematic based design example...
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This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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L5 - 1 Combinational Logic Design with Verilog ECE 152A...

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