L6 - Latches the D Flip-Flop Counter Design ECE 152A Fall 2006 Reading Assignment Brown and Vranesic 7 Flip-Flops Registers Counters and a Simple

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1 Latches, the D Flip-Flop & Counter Design ECE 152A – Fall 2006 October 24, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment ± Brown and Vranesic ² 7 Flip-Flops, Registers, Counters and a Simple Processor ± 7.1 Basic Latch ± 7.2 Gated SR Latch ² 7.2.1 Gated SR Latch with NAND Gates ± 7.3 Gated D Latch ² 7.3.1 Effects of Propagation Delays
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2 October 24, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment ± Brown and Vranesic (cont) ² 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) ± 7.4 Master-Slave and Edge-Triggered D Flip-Flops ² 7.4.1 Master-Slave D Flip-Flop ² 7.4.2 Edge-Triggered D Flip-Flop ² 7.4.3 D Flip-Flop with Clear and Preset October 24, 2006 ECE 152A - Digital Design Principles 4 Reading Assignment ± Roth ² 11 Latches and Flip-Flops ± 11.1 Introduction ± 11.2 Set-Reset Latch ± 11.3 Gated D Latch ± 11.4 Edge-Triggered D Flip-Flop
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3 October 24, 2006 ECE 152A - Digital Design Principles 5 Reading Assignment ± Roth (cont) ² 12 Registers and Counters ± 12.1 Registers and Register Transfers ± 12.2 Shift Registers ± 12.3 Design of Binary Counters ± 12.4 Counters for Other Sequences October 24, 2006 ECE 152A - Digital Design Principles 6 Combinational vs. Sequential Logic ± Combinational logic ² Function of present inputs only ± Output is known if inputs (some or all) are known ± Sequential logic ² Function of past and present inputs ± Memory or “state” ± Output known if present input and present state are known ² Initial conditions often unknown (or undefined)
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4 October 24, 2006 ECE 152A - Digital Design Principles 7 Gate Delays ± Recall from earlier lecture ² When gate inputs change, outputs don’t change instantaneously October 24, 2006 ECE 152A - Digital Design Principles 8 Feedback ± Outputs connected to inputs ² Single inverter feedback ± If propagation delay is long enough, output will oscillate
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5 October 24, 2006 ECE 152A - Digital Design Principles 9 Feedback ± If the propagation delay is not long enough, the output will settle somewhere in the middle ² V in = V out October 24, 2006 ECE 152A - Digital Design Principles 10 Feedback ± Ring Oscillator ² Any odd number of inverters will oscillate ± ½ period = total prop delay of chain
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6 October 24, 2006
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This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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L6 - Latches the D Flip-Flop Counter Design ECE 152A Fall 2006 Reading Assignment Brown and Vranesic 7 Flip-Flops Registers Counters and a Simple

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