{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

L6 - Latches the D Flip-Flop Counter Design ECE 152A Fall...

Info icon This preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Latches, the D Flip-Flop & Counter Design ECE 152A – Fall 2006 October 24, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.1 Basic Latch 7.2 Gated SR Latch 7.2.1 Gated SR Latch with NAND Gates 7.3 Gated D Latch 7.3.1 Effects of Propagation Delays
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 October 24, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) 7.4 Master-Slave and Edge-Triggered D Flip-Flops 7.4.1 Master-Slave D Flip-Flop 7.4.2 Edge-Triggered D Flip-Flop 7.4.3 D Flip-Flop with Clear and Preset October 24, 2006 ECE 152A - Digital Design Principles 4 Reading Assignment Roth 11 Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop
Image of page 2
3 October 24, 2006 ECE 152A - Digital Design Principles 5 Reading Assignment Roth (cont) 12 Registers and Counters 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other Sequences October 24, 2006 ECE 152A - Digital Design Principles 6 Combinational vs. Sequential Logic Combinational logic Function of present inputs only Output is known if inputs (some or all) are known Sequential logic Function of past and present inputs Memory or “state” Output known if present input and present state are known Initial conditions often unknown (or undefined)
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
4 October 24, 2006 ECE 152A - Digital Design Principles 7 Gate Delays Recall from earlier lecture When gate inputs change, outputs don’t change instantaneously October 24, 2006 ECE 152A - Digital Design Principles 8 Feedback Outputs connected to inputs Single inverter feedback If propagation delay is long enough, output will oscillate
Image of page 4
5 October 24, 2006 ECE 152A - Digital Design Principles 9 Feedback If the propagation delay is not long enough, the output will settle somewhere in the middle V in = V out October 24, 2006 ECE 152A - Digital Design Principles 10 Feedback Ring Oscillator Any odd number of inverters will oscillate ½ period = total prop delay of chain
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
6 October 24, 2006
Image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern