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L7 - Flip-Flops and Sequential Circuit Design ECE 152A Fall...

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1 Flip-Flops and Sequential Circuit Design ECE 152A – Fall 2006 October 31, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5.1 Configurable Flip-Flops 7.6 JK Flip-Flop 7.7 Summary of Terminology 7.8 Registers 7.8.1 Shift Register 7.8.2 Parallel-Access Shift Register
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2 October 31, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) 7.9 Counters 7.9.1 Asynchronous Counters 7.9.2 Synchronous Counters 7.9.3 Counters with Parallel Load 7.10 Reset Synchronization October 31, 2006 ECE 152A - Digital Design Principles 4 Reading Assignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) 7.11 Other Types of Counters 7.11.1 BCD Counter 7.11.2 Ring Counter 7.11.3 Johnson Counter 7.11.4 Remarks on Counter Design
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3 October 31, 2006 ECE 152A - Digital Design Principles 5 Reading Assignment Brown and Vranesic (cont) 8 Synchronous Sequential Circuits 8.1 Basic Design Steps 8.1.1 State Diagram 8.1.2 State Table 8.1.3 State Assignment 8.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions 8.1.5 Timing Diagram 8.1.6 Summary of Design Steps October 31, 2006 ECE 152A - Digital Design Principles 6 Reading Assignment Brown and Vranesic (cont) 8 Synchronous Sequential Circuits (cont) 8.2 State-Assignment Problem One-Hot Encoding 8.7 Design of a Counter Using the Sequential Circuit Approach 8.7.1 State Diagram and State Table for Modulo-8 Counter 8.7.2 State Assignment 8.7.3 Implementation Using D-Type Flip-Flops 8.7.4 Implementation Using JK-Type Flip-Flops 8.7.5 Example – A Different Counter
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4 October 31, 2006 ECE 152A - Digital Design Principles 7 Reading Assignment Roth 11 Latches and Flip-Flops 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with Additional Inputs 11.9 Summary 12 Registers and Counters 12.5 Counter Design Using S-R and J-K Flip-Flops 12.6 Derivation of Flip-Flop Input Equations – Summary October 31, 2006 ECE 152A - Digital Design Principles 8 The JK Flip-Flop Allows J = K = 1 condition Implemented with a gated SR latch and feedback of Q and Q* Q toggles (Q + = Q’) on J = K = 1
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