L8 - 1 Sequential Circuit Design with Verilog ECE 152A Fall...

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Unformatted text preview: 1 Sequential Circuit Design with Verilog ECE 152A Fall 2006 November 2, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment Brown and Vranesic 6 Combinational Circuit Building Blocks 6.6 Verilog for Combinational Circuits 6.6.1 The Conditional Operator 6.6.2 The If-Else Statement 6.6.3 The Case Statement 2 November 2, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters, and a Simple Processor 7.12 Using Storage Elements with CAD Tools 7.12.2 Using Verilog Constructs for Storage Elements 7.12.3 Blocking and Non-Blocking Assignments 7.12.4 Non-Blocking Assignments for Combinational Circuits 7.12.5 Flip-Flops with Clear Capability 7.13 Using Registers and Counters with CAD Tools 7.13.3 Using Verilog Constructs for Registers and Counters November 2, 2006 ECE 152A - Digital Design Principles 4 The Gated D Latch Transparent on high phase of clock module D_latch(D, Clk, Q); input D, Clk; output Q; reg Q; always @(D or Clk) if (Clk) Q = D; endmodule 3 November 2, 2006 ECE 152A - Digital Design Principles 5 The Gated D Latch The if construct When D or CLK change value: if CLK = 1, set Q = D Since there is no else, assignment occurs only when CLK = 1 Q follows D when CLK = 1 Q remains latched on CLK = 0 Always construct triggered by change in value of D or CLK Either change can cause the output to change November 2, 2006 ECE 152A - Digital Design Principles 6 The Gated D Latch The always construct Responds to changes in the signals on the sensitivity list always @ (D or Clk) Example above is level sensitive When D or Clk changes value Make edge triggered by using Verilog keywords posedge and negedge i.e., always @ (posedge Clk) 4 November 2, 2006 ECE 152A - Digital Design Principles 7 The Edge Triggered D Flip-Flop Positive edge triggered module flipflop(D, Clock, Q); input D, Clock; output Q; reg Q; always @(posedge Clock) Q = D; // Q + = D, characteristic function endmodule November 2, 2006 ECE 152A - Digital Design Principles 8 The Edge Triggered D Flip-Flop D is not included on sensitivity list since it cannot cause output (Q) to change...
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L8 - 1 Sequential Circuit Design with Verilog ECE 152A Fall...

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