L10 - Finite State Recognizers and Sequence Detectors ECE...

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1 Finite State Recognizers and Sequence Detectors ECE 152A – Fall 2006 November 9, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment ± Brown and Vranesic ² 8 Synchronous Sequential Circuits ± 8.4 Design of Finite State Machines Using CAD Tools ² 8.4.1 Verilog Code for Moore-Type FSMs ² 8.4.2 Synthesis of Verilog Code ² 8.4.3 Simulating and Testing the Circuit ² 8.4.4 Alternative Styles of Verilog Code ² 8.4.5 Specifying the State Assignment in Verilog Code ² 8.4.7 Specification of Mealy FSMs Using Verilog
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2 November 9, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment ± Roth ² 14 Derivation of State Graphs and Tables ± 14.1 Design of a Sequence Detector ± 14.2 More Complex Design Problems ± 14.2 Guidelines for Construction of State Graphs November 9, 2006 ECE 152A - Digital Design Principles 4 Mealy and Moore Machines ± Mealy Machine ² Output is a function of present state and present input ± Outputs valid on clock edge (transition) ² Simpler (possibly) ² Faster (possibly) ² Outputs “glitch” ² Used for synchronous (clocked) designs
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3 November 9, 2006 ECE 152A - Digital Design Principles 5 Mealy and Moore Machines ± Moore Machine ² Output is a function of present state only ± Outputs valid after state transition ² More “stable” than Mealy machine ± Outputs do not glitch ² Asynchronous (no clock) or synchronous designs November 9, 2006 ECE 152A - Digital Design Principles 6 Deterministic Recognizers ± State Diagram ² Also referred to as Deterministic Transition Graph ² Next state transition is determined uniquely by present state and present input ± Deterministic Recognizer ² Classifies input strings into two classes: ± Those it accepts ± Those it rejects
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4 November 9, 2006 ECE 152A - Digital Design Principles 7 Deterministic Recognizers ± Sequential Lock Analogy ² Accepted string corresponds to of the combination of the lock ± Accepted string opens the lock ± Rejected string leaves the lock closed ± Provides a basis for general purpose, finite state machine (FSM) design ² Controllers, peripheral interfaces, etc.
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This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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L10 - Finite State Recognizers and Sequence Detectors ECE...

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