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# L10 - Finite State Recognizers and Sequence Detectors ECE...

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1 Finite State Recognizers and Sequence Detectors ECE 152A – Fall 2006 November 9, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment Brown and Vranesic 8 Synchronous Sequential Circuits 8.4 Design of Finite State Machines Using CAD Tools 8.4.1 Verilog Code for Moore-Type FSMs 8.4.2 Synthesis of Verilog Code 8.4.3 Simulating and Testing the Circuit 8.4.4 Alternative Styles of Verilog Code 8.4.5 Specifying the State Assignment in Verilog Code 8.4.7 Specification of Mealy FSMs Using Verilog

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2 November 9, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment Roth 14 Derivation of State Graphs and Tables 14.1 Design of a Sequence Detector 14.2 More Complex Design Problems 14.2 Guidelines for Construction of State Graphs November 9, 2006 ECE 152A - Digital Design Principles 4 Mealy and Moore Machines Mealy Machine Output is a function of present state and present input Outputs valid on clock edge (transition) Simpler (possibly) Faster (possibly) Outputs “glitch” Used for synchronous (clocked) designs
3 November 9, 2006 ECE 152A - Digital Design Principles 5 Mealy and Moore Machines Moore Machine Output is a function of present state only Outputs valid after state transition More “stable” than Mealy machine Outputs do not glitch Asynchronous (no clock) or synchronous designs November 9, 2006 ECE 152A - Digital Design Principles 6 Deterministic Recognizers State Diagram Also referred to as Deterministic Transition Graph Next state transition is determined uniquely by present state and present input Deterministic Recognizer Classifies input strings into two classes: Those it accepts Those it rejects

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