L14 - Combinational Logic Building Blocks and Bus Structure...

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1 Combinational Logic Building Blocks and Bus Structure ECE 152A – Fall 2006 December 5, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment ± Brown and Vranesic ² 3 Implementation Technology ± 3.8 Practical Aspects ² 3.8.7 Passing 1s and 0s Through Transistor Switches ² 3.8.8 Fan-In and Fan-Out in Logic Gates ³ Tri-State Buffers (only this section of 3.8.8) ± 3.9 Transmission Gates ² 3.9.2 Multiplexer Circuit
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2 December 5, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment ± Brown and Vranesic (cont) ² 6 Combinational-Circuit Building Blocks ± 6.1 Multiplexers ² 6.1.1 Synthesis of Logic Functions Using Multiplexers ² 6.1.2 Multiplexer Synthesis Using Shannon’s Expansion ± 6.2 Decoders ² 6.2.1 Demultiplexers ± 6.3 Encoders ² 6.3.1 Binary Encoders ² 6.3.2 Priority Encoders ± 6.4 Code Converters December 5, 2006 ECE 152A - Digital Design Principles 4 Reading Assignment ± Roth ² 9 Multiplexers, Decoders and Programmable Logic ± 9.1 Introduction ± 9.2 Multiplexers ± 9.3 Three State Buffers ± 9.4 Decoders and Encoders
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3 December 5, 2006 ECE 152A - Digital Design Principles 5 Multiplexer ± Passes one of several data inputs to output ² Generally 2 n data inputs and always a single data output ² n control lines determine which input is “steered” to the output ± Allows logical (not “tri-state” or electrical) implementation of buses ² Buses and register transfer operations fundamental to digital system design December 5, 2006 ECE 152A - Digital Design Principles 6 Multiplexer ± Also possible to implement arbitrary combinational logic with multiplexers ² Universal, combinational logic element ± Also known as “Data Selector” and “Mux” ± In sequential operation, provides parallel to serial conversion
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4 December 5, 2006 ECE 152A - Digital Design Principles 7 Two-to-One Multiplexer ± F = Select’ · x 0 + Select · x 1 x1 = w0 ←→ X2 = w1 December 5, 2006 ECE 152A - Digital Design Principles 8 Four-to-One Multiplexer ± i th data input ANDed with minterm m i ² Embedded circuit generating minterms will become known as a decoder m 0 w 0 m 1 w 1 m 2 w 2 m 3 w 3
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5 December 5, 2006 ECE 152A - Digital Design Principles 9 Building Larger Multiplexers ± 4-to-1 (4:1) Mux using 2-to-1 (2:1) Muxes ² Simple and modular ² Adds 2 levels of gate (propagation) delay December 5, 2006 ECE 152A - Digital Design Principles 10 Building Larger Multiplexers ± 16:1 Mux constructed from 4:1 Muxes ² Expandable to 32:1 and 64:1 with additional 2:1 and/or 4:1 Muxes ± With additional levels of propagation delay
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This note was uploaded on 02/19/2012 for the course ENGR 361 taught by Professor Drexel during the Spring '12 term at Bloomsburg.

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L14 - Combinational Logic Building Blocks and Bus Structure...

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