# Lec3 - Karnaugh Maps Combinational Logic Design ECE 152A...

This preview shows pages 1–7. Sign up to view the full content.

1 Karnaugh Maps & Combinational Logic Design ECE 152A – Fall 2006 October 5, 2006 ECE 152A - Digital Design Principles 2 Reading Assignment ± Brown and Vranesic ² 4 Optimized Implementation of Logic Functions ± 4.1 Karnaugh Map ± 4.2 Strategy for Minimization ² 4.2.1 Terminology ² 4.2.2 Minimization Procedure ± 4.3 Minimization of Product-of-Sums Forms ± 4.4 Incompletely Specified Functions ± 4.8 Cubical Representation ² 4.8.1 Cubes and Hypercubes

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 October 5, 2006 ECE 152A - Digital Design Principles 3 Reading Assignment ± Roth ² 1 Introduction Number Systems and Conversion ± 1.4 Representation of Negative Numbers ± 1.5 Binary Codes ² 4 Applications of Boolean Algebra Minterm and Maxterm Expansions ± 4.5 Incompletely Specified Functions October 5, 2006 ECE 152A - Digital Design Principles 4 Reading Assignment ± Roth (cont) ² 5 Karnaugh Maps ± 5.1 Minimum Forms of Switching Functions ± 5.2 Two- and Three-Variable Karnaugh Maps ± 5.3 Four-Variable Karnaugh Maps ± 5.4 Determination of Minimum Expressions Using Essential Prime Implicants ± 5.5 Five-Variable Karnaugh Maps
3 October 5, 2006 ECE 152A - Digital Design Principles 5 Canonical Forms ± The canonical Sum-of-Products (SOP) and Product-of-Sums (POS) forms can be derived directly from the truth table but are (by definition) not simplified ² Canonical SOP and POS forms are “highest cost”, two-level realization of the logic function ² The goal of simplification and minimization is to derive a lower cost but equivalent logic function October 5, 2006 ECE 152A - Digital Design Principles 6 Simplification ± Reduce cost of implementation by reducing the number of literals and product (or sum) terms ² Literals correspond to gate inputs and hence both wires and the size (fan-in) of the first level gates in a two-level implementation ² Product (Sum) terms correspond to the number of gates in the first level of a two-level implementation and the size (fan-in) of the second level gate

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4 October 5, 2006 ECE 152A - Digital Design Principles 7 Simplification ± Algebraic Simplification ² Using theorems and properties of Boolean Algebra ± Difficult with large number of variables and complex Boolean expressions ± Most often incorporated into CAD Tools ± Karnaugh Maps ² Graphical representation of logic function suitable for manual simplification and minimization October 5, 2006 ECE 152A - Digital Design Principles 8 Two-Variable Karnaugh Map ± Location of minterms and maxterms on a two-variable map ² Index is the same, expansion is complementary 0 1 0 1 m 0 m 1 m 2 m 3 A B 0 1 0 1 M 0 M 1 M 2 M 3 A B
5 October 5, 2006 ECE 152A - Digital Design Principles 9 Two-Variable Karnaugh Map ± Simplification using xy + xy’ = x and x + x’y = x + y ² F= Σ m (0,2,3) 0 1 0 1 0 1 A B 1 1 F = A’B’ + AB’ + AB F = B’ (A’ + A) + AB F = B’ + AB F = (B’ + A) (B’ + B) F = B’ + A October 5, 2006 ECE 152A - Digital Design Principles 10 Three-Variable Karnaugh Map ± Location of three-variable minterms 0 1 00 01 A BC 11 10 m 4 m 5 m 7 m 2 m 3 m 1 m 0 m 6

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
6 October 5, 2006 ECE 152A - Digital Design Principles 11 Three-Variable Karnaugh Map ±
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 22

Lec3 - Karnaugh Maps Combinational Logic Design ECE 152A...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online