ECE344-Lecture13-Memory Management

ECE344-Lecture13-Memory Management - Lecture 13 Memory...

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1 Lecture 13: Memory Management David Lie ECE344 University of Toronto
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2 ECE344: Operating Systems Outline Introduction to memory management – Fragmentation – Paging Hardware Support Virtual Memory Translation Page Tables Linear, Multi-level and inverted Page Tables Memory Resource Tracking: – Bitmaps and Linked lists – The Coremap – The Address space structure – The stack, the heap and sbrk()
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3 ECE344: Operating Systems Dynamic Address Translation MMU needs to map page nr. to frame nr. on each memory reference – Conceptually, MMU is a table with an entry for each virtual page. • Each entry contains the frame number for the page – Each address coming from the processor is translated • Virtual page number is substituted with the physical frame number in its entry Where is all this translation information stored? MMU
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4 ECE344: Operating Systems Page Tables Virtual to physical address mappings are stored in a page table in memory A page table contains page table entries – Each entry has a mapping from a page to a frame – Each entry also contains various bits such as valid/invalid, dirty, etc. • Valid bit says whether mapping is valid or not • Other bits discussed later – Typically, each entry is one word
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ECE344: Operating Systems A Linear Page Table Example page table – Virtual address size: 16 bits – Page size: 12 bits – Nr. of pages: 16 (4 bits) – Physical address size: 15 bits – Nr. of frames: 8 (3 bits) – Page table entry size: 4 bits Example translation – vaddr = 0x2004 – offset – page = vaddr >> 12 = 0x2 – fr = page_table[page].addr = 6 – paddr = (fr << 12) | offset = 0x6004 Page table size? Valid bit
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ECE344-Lecture13-Memory Management - Lecture 13 Memory...

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