ECE344-Lecture15-Memory Management

ECE344-Lecture15-Memory Management - Lecture 15: Memory...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Lecture 15: Memory Management David Lie ECE344 University of Toronto
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 ECE344: Operating Systems Overview The TLB Miss Handler: Page Fault Handler Swap Handler Managing the Swap Area Paging issues and Performance Putting it all together. VM and OS events: – Process Creation, Copy-on-Write – Process Termination – Context Switching Memory mapped files and shared memory Modern Paging hardware: Superpages
Background image of page 2
3 ECE344: Operating Systems TLB Miss Handler Overview TLB Lookup TLB Miss Handler Page Fault Handler Miss Translate Hit Not in PT In PT TLB Write Allocate page, write to PT, may have to read from swap
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 ECE344: Operating Systems The TLB Interface Recall that MIPS has a software TLB handler. – This means that misses in the TLB raise an interrupt that is handled by a TLB Miss Handler in the OS. – A miss in the TLB is called a TLB Fault. Each TLB entry stores a virtual to physical mapping. An entry has two values: – EntryHI: contains the virtual page number half of the mapping – EntryLO: contains the physical frame number as well as permission bits – Entries are numbered by index numbers like an array
Background image of page 4
5 ECE344: Operating Systems The TLB Interface The OS161 TLB supports the following permission bits: – C bit: indicates whether that page should be cached in processor memory caches. You don’t really need to use this. – W/D bit: Even though it’s called a dirty bit, it’s really a write- able bit. Set this bit to let the process write to this page. Otherwise writes will result in a TLB Miss exception or TLB Fault. – V bit: Valid bit.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 02/20/2012.

Page1 / 16

ECE344-Lecture15-Memory Management - Lecture 15: Memory...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online