Lab3 - UNIVERSITY OF CALIFORNIA, DAVIS Department of...

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UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2012 LAB 3: COMBINATIONAL NETWORK DESIGN The purpose of this lab is to learn how to design a simple combinational logic network. Hardware Required : 1 74LS00 Quad 2-input NAND gate 1 74LS04 Hex INVERTER 3 74LS10 Triple 3-input NAND gate 1 74LS163 Synchronous Binary Counter 1 7-segment display and four current-limiting resistors Preparation (Pre-lab) ± Do the complete paper design of the NAND-NAND implementation of the combinational network specified in the lab write-up. Your paper design must include the following items: o K-maps for each of the 4 output signals, X1, X2, X7 and X6 o Minimized sum of products (SOP) equation for each output o Circuit representation using gates (i.e. schematic diagram) for the complete network using 3-input NAND gates, 2-input NAND gates, inverters and a 74LS163 binary counter. Description a) The basic problem specification is similar to Design Problem 8.S in your Roth text. However, we will change the animation pattern as described below. You will use the
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This note was uploaded on 02/21/2012 for the course EEC 180A taught by Professor Redinbo during the Spring '08 term at UC Davis.

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Lab3 - UNIVERSITY OF CALIFORNIA, DAVIS Department of...

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