Lab4 - UNIVERSITY OF CALIFORNIA, DAVIS Department of...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2012 LAB 4: COMBINATIONAL NETWORK USING MUXES AND CPLD In this lab, you will learn how to design and implement a combinational logic network using MSI chips such as adders and muxes. In Part II, you will implement two combinational logic designs in a Complex Programmable Logic Device (CPLD). We introduce a Hardware Description Language (HDL), Verilog, for specifying the circuit designs in Part II. Hardware Required : New parts: 1 74LS83 4-bit full adder 2 74LS153 Dual 4-to-1 multiplexers 1 MAN72A Seven-segment display 1 DIPswitch package DIPswitch with 4-switches 1 XC2C256 CPLD Xilinx CoolRunner-II CPLD on Digilent XC2-XL board Do not take the Digilent XC2-XL boards out of the lab. Preparation (Pre-lab) Do the complete paper design for Part I. Your paper design will have a complete truth table, K-maps and circuit diagrams using the multiplexers and the discrete logic gates. For each mux, have two designs ready. Part I: Using 4-Bit Adder, Muxes and Gates For this part, the 74LS83 4-bit adder will be used as a 2-bit adder, with the S3 output ( Σ 3 in 74LS83 datasheet) used as the carry. Design a combinational logic network which accepts the sum and carry from the 2-bit adder and displays the result on a seven-segment display. Figure 1 shows a block diagram of the desired circuit. Note that only the numbers 0 to 6 need to be displayed, thus requiring only a total of 6 unique output functions (Verify and explain). Design and implement four of these 6 output functions by using four 4-to-1 multiplexers and the other two by using logic gates, restricted to gates available in your kit. For each multiplexer used, show two designs with different sets of variables used on the selection inputs! Your TA will decide which design you will implement in the lab. Be sure to have your TA verify your working circuit. Also remember to connect a current-limiting resistor to each segment of the seven-segment display. Show your calculations for a current-limiting resistor that limits the current to about 8 mA. Data sheets are available through the course website.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 4-Bit Adder A 1 A 2 B 1 B 2 MUX and Combinational Network S 1 S 2 S 3 (Carry) 7-Segment Display 7 Figure 1: Part I Block Diagram Part II: Using Xilinx Complex Programmable Logic Device (CPLD) In this part of the lab, you will use a CPLD to implement a combinational logic circuit. You will use Verilog to specify your combinational circuit based on a simple example. For this lab, you will not need to learn Verilog in depth, but you will learn how to specify basic combinational circuits. Design Specifications You will use a 4-switch DIPswitch as input and a 7-segment display as output of the Xilinx CPLD board, as described in detail later in this lab. Switch[3] will determine the mode of your circuit.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 10

Lab4 - UNIVERSITY OF CALIFORNIA, DAVIS Department of...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online