This preview shows pages 1–3. Sign up to view the full content.
1
UNIVERSITY OF CALIFORNIA, DAVIS
Department of Electrical and Computer Engineering
EEC180A
DIGITAL SYSTEMS I
Winter
2012
LAB 4: COMBINATIONAL NETWORK USING MUXES AND CPLD
In this lab, you will learn how to design and implement a combinational logic network using MSI
chips such as adders and muxes. In Part II, you will implement two combinational logic designs in
a Complex Programmable Logic Device (CPLD). We introduce a Hardware Description
Language (HDL), Verilog, for specifying the circuit designs in Part II.
Hardware Required
:
New parts:
1
74LS83
4bit full adder
2
74LS153
Dual 4to1 multiplexers
1
MAN72A
Sevensegment display
1
DIPswitch package
DIPswitch with 4switches
1
XC2C256 CPLD
Xilinx CoolRunnerII CPLD on Digilent XC2XL board
Do not take the Digilent XC2XL boards out of the lab.
Preparation (Prelab)
•
Do the
complete
paper design for Part I. Your paper design will have a complete truth
table, Kmaps and circuit diagrams using the multiplexers and the discrete logic gates.
For
each mux, have two designs ready.
Part I: Using 4Bit Adder, Muxes and Gates
For this part, the 74LS83 4bit adder will be used as a 2bit adder, with the S3 output (
Σ
3 in
74LS83 datasheet) used as the carry.
Design a combinational logic network which accepts the
sum and carry from the 2bit adder and displays the result on a sevensegment display. Figure 1
shows a block diagram of the desired circuit.
Note that only the numbers 0 to 6 need to be displayed, thus requiring only a total of 6 unique
output functions (Verify and explain).
Design and implement four of these 6 output functions by
using
four
4to1 multiplexers and the other two by using logic gates, restricted to gates available
in your kit.
For each multiplexer used, show
two
designs with
different
sets of variables used on the selection
inputs!
Your TA will decide which design you will implement in the lab.
Be sure to have your
TA verify your working circuit.
Also remember to connect a currentlimiting resistor to
each
segment of the sevensegment
display. Show your calculations for a currentlimiting resistor that limits the current to about 8
mA. Data sheets are available through the course website.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document2
4Bit
Adder
A
1
A
2
B
1
B
2
MUX
and
Combinational
Network
S
1
S
2
S
3
(Carry)
7Segment
Display
7
Figure 1:
Part I Block Diagram
Part II: Using Xilinx Complex Programmable Logic Device (CPLD)
In this part of the lab, you will use a CPLD to implement a combinational logic circuit. You will
use Verilog to specify your combinational circuit based on a simple example. For this lab, you will
not need to learn Verilog in depth, but you will learn how to specify basic combinational circuits.
Design Specifications
You will use a 4switch DIPswitch as input and a 7segment display as output of the Xilinx CPLD
board, as described in detail later in this lab. Switch[3] will determine the mode of your circuit.
This is the end of the preview. Sign up
to
access the rest of the document.
 Spring '08
 REDINBO

Click to edit the document details