# Lab5 - UNIVERSITY OF CALIFORNIA DAVIS Department of...

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1 UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2012 LAB 5: STATIC HAZARDS, LATCHES AND FLIP-FLOPS Objective The first topic in this lab is static hazards, which can cause a circuit to malfunction. You will build and test a circuit with a static hazard and then redesign the circuit to eliminate the static hazard. The main objective of this lab is to introduce the basic circuit elements, known as flip-flops and latches, which are used to design sequential circuits. Unlike the combinational circuits in the previous labs, sequential circuits have outputs that depend on the past input sequence as well as the present inputs. Flip-flops and latches are simple memory devices that can maintain, or “remember” an output state even after the input that caused it has changed. You will learn how these memory devices can be built from logic gates. Hardware Required 4 74LS00 Quad 2-Input NAND Gates 2 74LS04 Hex Inverters 1 74LS10 Triple 3-Input NAND Gates 1 74LS125 Quad Tri-State Buffers Preparation Analyze the function Y = SEL * A + SEL’ * B using a Karnaugh map. Determine if this function has a static 0-hazard or a static 1-hazard. Using the K-map, derive an equation which implements the same function but eliminates the static hazard. Using only parts available in the Hardware Required list (above), redesign the circuit shown in Figure 1 to eliminate the static hazard. Be prepared to build this circuit in the lab. For the circuit of Figure 2, construct a transition table summarizing the operation of the circuit. This table will show all possible “current” values for A, B, X, and Y , and also the resulting “next” values for X and Y. Make a transition table for the clocked S-R latch circuit shown in Figure 4. Part I.

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Lab5 - UNIVERSITY OF CALIFORNIA DAVIS Department of...

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