lab6 - UNIVERSITY OF CALIFORNIA, DAVIS Department of...

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UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2012 LAB 6: COUNTER DESIGN Objective: Given a desired counting sequence, design and build the counter using flip-flops and gates. Derive the flip-flop input equations using a state table and K-maps Hardware Required : 2 74LS74 D flip-flop 1 74LS47 BCD to 7-Segment Decoder/Driver 1 7-segment display and 7 current-limiting resistors 1 SPDT switch x 74LS00, 74LS04, 74LS10 logic gates ( as needed – try to use as few as possible! ) Preparation (Pre-lab) Do the complete paper design for the counter specified in Design I. Your paper design must include the following items: o State transition table for the counter o K-maps for each of the flip-flop input equations. o Minimized sum of products (SOP) equation for each flip-flop input signal. Description In this lab, you will design a unique counter that implements the state diagram shown in the figure below. Each student will be given an individualized count sequence to implement. (See
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This note was uploaded on 02/21/2012 for the course EEC 180A taught by Professor Redinbo during the Spring '08 term at UC Davis.

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lab6 - UNIVERSITY OF CALIFORNIA, DAVIS Department of...

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