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homework_verilog_problem

homework_verilog_problem - input[3:0 icode output need_valC...

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wire [ 3: 0 ] icode; wire [ 3: 0 ] ifun; wire [3: 0] rA; wire [3:0] rB; wire [31: 0] valC; wire [31: 0] PC; wire [31: 0] valP; wire need_valC; wire need_regids; module set_need_regids( icode ); input [3:0] icode; ouput need_regids; parameter registers1 = 4'h2; parameter registers2 = 4'h6; parameter a_register1 = 4'hA; parameter a_register2 = 4'hB; parameter both1 = 4'h3; parameter both2 = 4'h4; parameter both3 = 4'h5; assign need_regids = registers1 || registers2 || a_register1 || a_register2 || both1 || both2 || both3 ? 1 : 0; endmodule module set_need_valC( icode);
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Unformatted text preview: input [3:0] icode; output need_valC; parameter val1 = 4'h7; parameter val2 = 4'h8; parameter both1 = 4'h3; parameter both2 = 4'h4; parameter both3 = 4'h5; assign need_valC = val1 || val2 || both1 || both2 || both3 ? 1 : 0; endmodule module pc_increment(PC, icod, ifun, valC, need_valC, need_regids, valP); input [31: 0] PC; input need_valC; input need_regids; output [31: 0] valP; assign valP = PC + 1 + 4*need_valC + need_regids; endmodule...
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