Comp Arch - parameter a_register1 = 4'hA; parameter...

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Comp Arch 9.11 A. Virtual Addres 0x027c 00 0010 0111 1100 0 0 0 0 1 0 0 1 1 1 1 1 0 0 B. VPN: x09 TLB index: x01 TLB tag: x02 TLB Hit?: No Page Fault? : N PPN: 0x17 C. Physical Address 0101 1111 1100 D. CO: 0x0 CI: 0x0f CT: 0x17 cache hit? N cache byte? - 7.6 Symbol Swap.o .symtab entry? Symbol type Module where defined Section Buf Yes Extern Main.o .data Bufp0 Yes global Swap.o .data Bufp1 Yes local Swap.o .bss swap Yes global Swap.o .text temp No - - - incr Yes local Swap.o .text count Yes local Swap.o .data 6.31 A. 128 bytes B. CT CT CT CT CT CT CT CT CI CI CI CO CO 6.32 A. 0 0 1 1 1 0 0 0 1 1 0 1 0
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B. Block Offset (CO): 0x2 Index (CI): 0x6 Cache Tag (CT): 0x38 Cache Hit? : Yes Cache byte Returned? : 0xEB Verilog wire [ 3: 0 ] icode; wire [ 3: 0 ] ifun; wire [3: 0] rA; wire [3:0] rB; wire [31: 0] valC; wire [31: 0] PC; wire [31: 0] valP; wire need_valC; wire need_regids; module set_need_regids( icode ); input [3:0] icode; ouput need_regids; parameter registers1 = 4'h2; parameter registers2 = 4'h6;
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Unformatted text preview: parameter a_register1 = 4'hA; parameter a_register2 = 4'hB; parameter both1 = 4'h3; parameter both2 = 4'h4; parameter both3 = 4'h5; assign need_regids = registers1 || registers2 || a_register1 || a_register2 || both1 || both2 || both3 ? 1 : 0; endmodule module set_need_valC( icode); input [3:0] icode; output need_valC; parameter val1 = 4'h7; parameter val2 = 4'h8; parameter both1 = 4'h3; parameter both2 = 4'h4; parameter both3 = 4'h5; assign need_valC = val1 || val2 || both1 || both2 || both3 ? 1 : 0; endmodule module pc_increment(PC, icod, ifun, valC, need_valC, need_regids, valP); input [31: 0] PC; input need_valC; input need_regids; output [31: 0] valP; assign valP = PC + 1 + 4*need_valC + need_regids; endmodule...
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This note was uploaded on 02/21/2012 for the course ECE 452 taught by Professor Parashar during the Spring '08 term at Rutgers.

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Comp Arch - parameter a_register1 = 4'hA; parameter...

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