EEE4306_Quiz_3_Solution_2011

# EEE4306_Quiz_3_Solution_2011 - EEE 4306 QUIZ III 100 Points...

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Unformatted text preview: EEE 4306 QUIZ III, 100 Points Name: ‘ k 60 Minutes. Open Note, Open Book, 3/4/11 UFID . (5 points) Circuit Element Values, RE = 50 Q, R5 = 500 Q, RDD = 75K Q, RL = 1K Q, CA = 10 pF, C3 = 10 pF, Cx =’10 pF, CY = ooF C5 = ooF. Assume CA, CB and CX represent all the capacitance from the transistors at those nodes. PNP BJT Parameters: B = 75, VA = 75V, BJT base-emitter VBBON E 0.7V Assume and PNP BJT devices (Q1, Q2, and Q6) are in linear active. NFET MOS Parameters: VTN= 1 V, k = 8mA/V2= l/2unCox(Wn/Ln), and, 9» = 0.04. Assume that the NMOS (M3, M4, M5, M7, Mg, and M9) are in saturation. Also, assume that IDS is set to be the same as the current set by the bias circuit at the source 135 of M5 because the base current of Q; is added to it. VSUPPLY = 15V a) Biasing Calculations: (5 points): Find Ry so that the differential pair has 4 mA bias through the NMOS current source, Mg. li—ch7v'/5 ‘ v35: V497: \4, = VT». 1/5 RY=—£p—- ._, 7,ka; . ‘7 Ir ’ ‘ I/V'f‘. L/m/l ... 54.7073” syn/Muz— qm/t :/+1/;:/,Zﬂ7 :: 3m A/l/ b) Find the midband Stage 1 small signal stage gain, the Stage two gain and the “G ' ,(70 ' t). overa am poms c : gm} 2 V [+9m3'es “Fur/M,- fab/L AStagel : A = /Z. R Vlnl—VZ —— f: 1lléwt/At/V’ ‘7’7/r/L In _ﬁ'__é. : :7Sv/\/ W 77} ' 9mg" JQ/VIé 2,” V0 BE 54; 025 As,g2=7= 9m «8 ,0 ‘ :2 935111 A 5 543 resfbngés “‘ 'ﬂ 3m14ﬂ-g7kv 97334 0L]- 7L gm7ﬂ5> : [ZSLL \$982] 5: V 5 g1 L A pr/(f +92%! R3) A0verall=Vn _0Vm2: ('- 50,?) / z VZ/j’gzyV/V ‘ rﬂyxzmﬂ (“LEM/{4' 50%) :: éZ-§/t fl 9m; 49%; vq-XmA/wm @ ( ’35 Z “ r04 E0 E +1» C // 3m ’5 h}?— Kg :75’ ( 5 ’f 'f‘ O IQLEQS : 1200 £95 Kali; ZMA 7; 77/:J7Jlé1zsfull 7536/; Z /X7r&/L : 93’4h/L R 617/9137'51 _<=<.2 _L I Lag/“5&9 // £62” of; 8“; ‘xrp: oL/w/mA/u-‘Q’WL 2 1‘” kﬂ‘ 5.51166 :0 pm ; mm; @ (AMI! Ii) hm my :- 75’ 7hum 1; til: :2 75km c) DRAW a Cc on the circuit that gives the best (highest level) of compensation to the op amp. (5 Points) (1) Pick the Cc value from part c) above to set your (01:1 to 20a rad/s. Show why or why not the circuit phase margin is > 45 degree (15 points). I (Up 2 I” 9 R ' Q “ﬁg/329M: ms 'Q 2‘ ) 2mm 763ka » sit/lazy IIVB‘m/‘l/l/ :ién/r CC: )5 a; : A‘Wkl : 20777 Law": 2295/3 ‘: nglpirzg 1’ C Mica“ Zing—*2 Q ._. 53W (C:i64p. r 2 +C¢ (q HE) R 9V 8 //. 3m/4/V a Qé‘n/c W cm C5 . €59? F)(/ﬂpF) ~/- fiénFﬂaf, «Ha/9 F) ; iéx [DEV/S 1) Bonus: What is the maximum DC Vin = Vinl = Vin; and minimum Vin = Vinl = Vin; that can be applied and still have the circuit amplify in small signal? (5 points). DAV; AAA? : Vpr/y - VBE.’ "" :12,“ left ~ V95, Vésj : i§\/_0,7V“ZM/4';"JZ—_J%+ : [5(Z\/ 1+ %=/.;v VDCMM/ ___ visov ﬁvéé:+_lggrf063jl+ VDSK- 21/ 2 45¢ + i +:_.'1V‘+u:§§\$;/V : ”//’ [vSV ...
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EEE4306_Quiz_3_Solution_2011 - EEE 4306 QUIZ III 100 Points...

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