{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

# CO-four - Unit-IV Computer Arithmetic Addition and...

This preview shows pages 1–10. Sign up to view the full content.

Unit-IV Computer Arithmetic Addition and subtraction Multiplication algorithms Division algorithms Floating point arithmetic operations Decimal arithmetic unit Decimal arithmetic operations

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Addition and subtraction with signed-magnitude data Addition algorithm : When the signs of A and B are identical , add the magnitudes and attach the sign of A to the result. When the signs of A and B are different , compare the magnitudes and subtract the smaller number from the larger. Case 1 : Choose the sign of the result to be the same as A if A > B Case 2 : Choose the sign of the result to be the complement of the sign of A if A < B. Case 3 : If the two magnitudes are equal, subtract B from A and make the sign of the result positive.
Examples Ex: (+2) + (+3) = +5 Ex : (-2) + (-3) = (-5) Ex: (+3) + (-2) = +1 Ex: (-2) + (+3) = +1 Ex : (+3) + (-5) = (-2) Ex : (-5) + (+3) = (-2)

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Subtraction algorithm When the signs of A and B are different , add the magnitudes and attach the sign of A to the result. When the signs of A and B are identical , compare the magnitudes and subtract the smaller number from the larger. Case 1 : Choose the sign of the result to be the same as A if A > B Case 2 : Choose the sign of the result to be the complement of the sign of A if A < B. Case 3 : If the two magnitudes are equal, subtract B from A and make the sign of the result positive.
Examples Ex: (-2) - (3) = (-5) Ex : (2) - (-3) = (5) Ex: (3) - (2) = 1 Ex: (2) - (3) = -1 Ex : (-3) - (-5) = 2 Ex : (-5) - (-3) = -2

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Hardware implementation B Register Complementer Parallel adder E A Register AVF A s M (mode control) B s Load sum Output carry
Hardware implementation The addition of A and B is done through parallel adder. The S (sum) output of the adder is applied to the input of the A register. The complementer provides an output of B or the complement of B depending on the state of the mode control M . The M signal is also applied to the input carry of the adder. When M=0, the output of B is transferred to the adder, the input carry is 0, and the output of the adder is equal to the sum A+B. When M = 1, the 1’s complement of B is applied to the adder, the input carry is 1, and output S = A + B +1 . This is equal to A plus the 2’s complement of B, which is equivalent to the subtraction A – B . ¯

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Addition and subtraction with signed 2’s complement data In signed 2’s complement representation, the leftmost bit of a binary number represents the sign bit: 0 for positive and 1 for negative. If the sign bit is 1, the entire number is represented in 2’s complement form. Ex. +33 is represented by 0 0 1 0 0 0 0 1 and -33 is represented by 1 1 0 1 1 1 1 1 Note : 1 1 0 1 1 1 1 1 is 2’s complement of 0 0 1 0 0 0 0 1 and vice versa.
Contd., The addition of two numbers in signed-2’s complement form consists of adding the numbers with the sign bits treated the same as other bits of the number.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 33

CO-four - Unit-IV Computer Arithmetic Addition and...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online