CO-four - Unit-IV Computer Arithmetic Addition and...

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Unit-IV Computer Arithmetic Addition and subtraction Multiplication algorithms Division algorithms Floating point arithmetic operations Decimal arithmetic unit Decimal arithmetic operations
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Addition and subtraction with signed-magnitude data Addition algorithm : When the signs of A and B are identical , add the magnitudes and attach the sign of A to the result. When the signs of A and B are different , compare the magnitudes and subtract the smaller number from the larger. Case 1 : Choose the sign of the result to be the same as A if A > B Case 2 : Choose the sign of the result to be the complement of the sign of A if A < B. Case 3 : If the two magnitudes are equal, subtract B from A and make the sign of the result positive.
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Examples Ex: (+2) + (+3) = +5 Ex : (-2) + (-3) = (-5) Ex: (+3) + (-2) = +1 Ex: (-2) + (+3) = +1 Ex : (+3) + (-5) = (-2) Ex : (-5) + (+3) = (-2)
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Subtraction algorithm When the signs of A and B are different , add the magnitudes and attach the sign of A to the result. When the signs of A and B are identical , compare the magnitudes and subtract the smaller number from the larger. Case 1 : Choose the sign of the result to be the same as A if A > B Case 2 : Choose the sign of the result to be the complement of the sign of A if A < B. Case 3 : If the two magnitudes are equal, subtract B from A and make the sign of the result positive.
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Examples Ex: (-2) - (3) = (-5) Ex : (2) - (-3) = (5) Ex: (3) - (2) = 1 Ex: (2) - (3) = -1 Ex : (-3) - (-5) = 2 Ex : (-5) - (-3) = -2
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Hardware implementation B Register Complementer Parallel adder E A Register AVF A s M (mode control) B s Load sum Output carry
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Hardware implementation The addition of A and B is done through parallel adder. The S (sum) output of the adder is applied to the input of the A register. The complementer provides an output of B or the complement of B depending on the state of the mode control M . The M signal is also applied to the input carry of the adder. When M=0, the output of B is transferred to the adder, the input carry is 0, and the output of the adder is equal to the sum A+B. When M = 1, the 1’s complement of B is applied to the adder, the input carry is 1, and output S = A + B +1 . This is equal to A plus the 2’s complement of B, which is equivalent to the subtraction A – B . ¯
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Addition and subtraction with signed 2’s complement data In signed 2’s complement representation, the leftmost bit of a binary number represents the sign bit: 0 for positive and 1 for negative. If the sign bit is 1, the entire number is represented in 2’s complement form. Ex.
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This note was uploaded on 02/23/2012 for the course CS 101 taught by Professor Martand during the Spring '10 term at Punjab Engineering College.

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CO-four - Unit-IV Computer Arithmetic Addition and...

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