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Unformatted text preview: CompE 270 Digital Systems Sp12 NAME: 50 ikféf Exam 1  use additional sheets or other side if needed  SHOW YOUR WORK!! 1) Add the 8—bit values (show results as 8 bits binary, hex, and decimal. 10 pts Add hex: convert&add binary: convert 2s comp to decimal
l I 1 I l i 1
B3 hex 1 Q L L l l 1 9 binary : “é»é Signed Dec
+ 52 hex + O l O i O U I 0 binary :“PEBZ— Signed Dec
show __'44W7_47 ___________444447 __74i
results in = O] O 010 O a 0 binary :+ J g Signed Dec
hexadeCimal: ( =i) [(3 hex convert hex to Is the 2’s comp Result valid? <:}/ Ni Signed decimal: 4'ié3
_ Is the unsigned Result valid? Y /IN1_
Carry Out: C : 1 Overflow: ND??— 2) Binary notation has a range of valid values which depends on the number of
bits and format. What is the range of valid values (in decimal) for:
2 pts. ea 5 bits, unsigned 5 bits, 2’s complement
(most 4 6T
from: C) (base 10) negative) from: “2 1;" "/é(base 10)
g OR. 4 Or
to: " :13) (base 10) (to most to:+?:" 5 +[Si(base 10)
positive) Fuel“
3) multiply 6m times llm in unsigned binary: ll 1(2 L i
5 pts YOU MUST Show partial products!
x_ Q l i Q
Q 9 Q Q
1
L E l 1
I.
L Q l L
Result: 1 o O 0 O l 0 check166?
4) Convert the following numbers: 6*, %_2# = 6&3
(2 pts ea)
a) 4 bit 2’s comp: ll.lle . l b) Signed 8 bit hex 80 u
to decimal: “0&5 W92}: to decimal: h" c) Decimal —l.75 d) Decimal 63 f,
to 4 bit 2’s comp binary: (EXCD) to unsigned hex: ng: “Z + 0.23“ 5) Calculate the following using 4~bit BCD sum using binary addition,
correction and show the decimal equ1valents:
1 1” 5 pts 0 0 l l O l l 1 ECU = 37 Decimal +0 1 0 1 0 1 0 1 BCD = Decimal
{DOD [EGO
+ I l O Result 5C>§;\ €><> 1C) BCD : iwz Decimal CompE 270 NAME: \Xi3x§?< 3 Exam 1 6) For the equations below:
Draw circles for both functions on the Karnaugh maps below
10 pts ‘4 yz
(X+Y)(X’+Z)(Y+Z) \\\ ’”"4”\
X DD 0! [l )0 (X+Y)(X’+Z) yz 7L
x (90 of I! (C
£>
x([
\k_,ah5’/
ﬂ 7) For the following Kmap, fill in the truth table and:
25 pts total Min/Maxterms (4 pts) List Minterms: 2 111(6) fjé8jqu5) + d(%:{ [ELM—t Maxterms: H M( 3/4/biig074] 2 l ' d(’C§Ll"§JIﬂ Include don’t care terms above. Label the columns and rows of the Kmap [lpt),
and fill in the truth table: (5 pts) csmwwm+m¢“o
iiiﬁiﬁilﬁiﬁiﬁilﬂ ~.i‘ a
w ram Now minimize the logic using the Kmap, and
Write the simElified SOP form of the eqn:
(5 pts) y = k9C: 4' EJCZ; With the simplified SOP equation above, what will the y output be for each of
the don’t care conditions?
(5 pts) Don’t care term #3 that are ls: Don’t care term #5 that are 05: 31+ 2m 270Exam18p12doc 2 CompE 270 NAME:
Exam 1 8) Fill in the Sum and Carry outputs based on the inputs for the Circuit with four full adders plus the gates shown:
20 pts total
X3 1 Am Bun X2 Y3 X1 Y1 X0 Y0 AIn Bin Am Bln
Gout Cln Gout Cin
SUM SUM c +Cout Cin ST” 1 1
Z; 21 Zn
ADD SDG jug HUD
Inputs M = O l, I, l I O
, (111
X : 0110 0011 0111 1111
Y : +0001 “0101 F 1000 +0001 Outputs 2 = OHL z: 11 to Z: 1 l 1” Z: 000:;
{DW (:0th C : O c: I c: 5 C: ‘1 P1 20 pts total O:OFF l=ON A B C F A B C F
o o 0 o o o 0 o
0 0 1 1 0 o 1 5:
0 1 0 o 0 1 0 o
o 1 1 1 0 1 1 I
1 0 o 5 1 0 0 c,
1 0 1 i 1 0 ﬂi
1 1 O 5 l l 0 O
41“ 1 1 _17 1 1 1 1 :\ 5081’qu (1073 What is the function of the4bf‘ie1‘épht? (&+y3)';?_f 9) Fill in the truth tables and the equation for the circuits below: : 13"»
+
(‘1
tg>
E)
o
2
13
i.
(F
r\ 270Exam18p12000 3 CompE 270 NAME: Exam 1 10) True/False 1 pt each T/F Equation T/F Equation a" I ) _———" : x'+x'=/1/,>g L Xoo=0 Ix+x=x ‘E xx0R1:x’ E X+X’:,}?’} E; X'X’VXKCD j:— (X+Y+Z) : (X'Y'Z')' I x + YZ = (x + Y) (x + 2) CJt‘sTLnJLJ I XY+X‘Z+YZ:XY+X'Z : (X+YJ[X' +ZJ=XZ+X'Y
CmmAﬁg‘) [email protected] + _ _ HEVASCF me E
II) Convert the follow1ng binary values to A i L
‘ _ 00 NUL 23 + 56 v
an ASCII character string, u51hg the hex m SOH 2C ‘ 57 W
ASCII table to the right. 02 STX 20 A 58 X
03 ETX 2E . 59 v
10 pts 04 EOT 2F / 5A Z
05 ENQ 30 o 58 [
COnvert the ASCII symbols: 05 ACK 31 1 50 \
07 BEL 32 2 5D ]
Compmm 05 BS ‘ ~ 33 3 SE A t
09 HT 34 4 SF — t
.  Y . 0A LF " 35 5 50 \
To Hex. and binary. DB VT 36 6 51 a
DC FF 3? 7 52 b
C 4; Job 00” 00 CR 33 a 63 c
 0E so 39 9 54 I21
O42? [lgllwi FSi 3A: 659
‘ m DLE as ; 66 i
m E07 ] 3 Q 1 [Di :1 DC1 (XON) ac c: 67’ g
“ "—' w2 002 (TAPE) 30 = 55 i1
p 20 J l l 0000 13 D03 (XaDFF) 3E > 69 i
f 14 004 iﬂPEr 3F 7 6A j
E f ()0 0 to 15 NAK 40 Q SB 1:
ﬂ: \ we SYN 41 A so I
0 D f a) 17 ETB 42 B 50 m
2 t l o 18 CAN 43 0 SE n
a l 19 EM 44 D F o
7 3? 0\ l‘ [ t : sua 45 E 70 p
18 E80 45 F 71 q
0 3L WC F8 47 G 72 r
:0 GS 43 H 73 5
1E RS , 49 s 74 1
Be sure to use correct upper/lower case! 1? LS 4A J 75 u
H 20 SF’ 48 K 76 v
ASCII Codes 48 , + 69; ~ ell: 97‘ ! 40 L 77 w
1F IU 3p ‘7 22 " . 4D M 78 X
f 23. # 4E N 79 y
0662/ 24 s 4F 0 7A 2
25 % 50 P 7E! [
low 25 a 51 Q 70 L
2? I 52 R m }
28 ( 53 3 TE ~
29 ) 54 T 7F DEL
2A “ 55 U 270Exam1Sp12.d0c 4 CompE 270
Exam 1 12) A digital input data stream is noisy, so each incoming bit is sampled 4
times, with the expectation that most of the samples will represent the
correct value. The 4 noisy samples of each bit are evaluated and if there are
more ones than zeros, we want to output a one, and if there are more zeros
than ones, then the output should be zero. If there are an equal number of
zeros and ones, then the output is not valid. You must design a combinational logic block that has four inputs A, B, C, D,
representing the four input samples, and it must output two bits: The first
output is F. F:l if the majority of the four inputs A—D are one, and F:O if
the majority of the inputs are zero. The other output is V (for Valid) to
indicate whether the F output is correct. V=l when three or four of the input
bits are the same, indicating that there is a majority of ls or Os and the F
output is valid. The output V=O when two of the input bits =l and the other
two bits :0. When V:O, output F is a don’t care. For example, if ABCD=lllO, 3 of the 4 input bits received are ls, so F:l, and
V:l. Likewise, if ABCDZOOlO then F:O and V:l, since 3 of the 4 inputs are
zeros. If ABCD:OlOl, then the 4 received samples have an equal number of ls
and 05 (two ls and two Os), so the “Valid” output signal V:O, and Fax since we
we don’t care what the F output is because it’s not valid. Draw the block diagram showing inputs and outputs below, and on the next page,
fill in the rest of :he truth tables and Kemaps, minimize the logic, write the
equations for F and V, and draw the design using AND gates, OR gates, and
inverters, to generate the outputs as described above. Use the following page and additional sheets to do your design. xx pts Remember: it’s most important to show the correct design process! Block diagram: M L3)" I) 6‘3‘LPOigbbL €125 “CfV £®#‘M \ 5 pts Using the information on the next page, write the
Minimized SOP equation for F: 5 pts F : db 4— ea. 270Exam18p12.doc 5 CompE 27o NAME: {CD/UTILQW—A Exam 1 12) (cont’d) Truth Tables and K Maps for F and V: fill in the missing entries 2 pts for completing table 8 pts for Kmap A B C D F
(DI—O 0 o 0 0
I 0 0 0 1 0
2 0 0 1 0 0
g 0 O 1 1 X
4 0 1 0 O 0
g 0 1 0 1 X
é 0 1 1 0 x
7 0 1 1 1 I
g 1 0 0 0 g)
‘1 1 0 0 1 X
lo 1 0 1 o x
H 1 O 1 1 1
[2, 1 1 o 0 x
L”) 1 1 0 1 1 1 1 1 0 1
’5’ 1 1 1 1 1 Draw F gates: 5pts SOP fbrm 2 pts for completing table 8 pts for Kmap A B C D V
0 0 0 0 0 1
J 0 0 0 1 1
1 0 0 1 0 1
3, 0 o 1 1 0
4. 0 1 0 0 1
S” 0 1 0 1 0
b 0 1 1 o p
7 0 1 1 1 [
g 1 o 0 0 {
q 1 0 0 1 D
to 1 0 1 0 O
{1 1 o 1 1 1
[Z 1 1 0 0 0
{3 1 1 r0 1 1
{5. 1 1 1 0 1 ‘
{‘3’ 1 1 1 1 1 Mo ngamk (351 ¢L><$éﬂrwu
Minimized POS equation for V: UALﬁe+V 06* LEEL&5}LL 3 5 pts ’ I f I I J I I I e I
v = P1+B+C+D AJB+C4~DYH+®+C+D¥A+MC4D>(£1+_6*C*U 9+8 +010}
0011 (>101 0110 [001 1010 Mai)
<; :5 5’ Q} ﬁ “3 [2f 270Exam18p12doc 6 ...
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This note was uploaded on 02/26/2012 for the course COMPE 270 taught by Professor Harris during the Spring '08 term at San Diego State.
 Spring '08
 HARRIS

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