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270Exam2Sol

# 270Exam2Sol - CompE 270 Digital Systems Spll NAME g0 Exam#2...

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Unformatted text preview: CompE 270 Digital Systems Spll NAME: g0 Exam #2 — use additional sheets if needed —— SHOW WORK for partial credit 1) The diagrams below show Mealy and Moore state machines. Identify which type, and the maximum number of states each could implement if each has 5 FES. lO_pts Binary state empoding: Onewhot state encoding: Combinaiional Subcircuil {For Outputs: Combinational Subcircuii (For Flip-Flop In uls 0‘: Fl ] Combinatia rial Zn Su bcircuil Clock Clock Circle (5) Type: Mealy / Type: / Moore @Maximum ii states: 32: ®Maximum ii states: 5/ 2} Fill in the rest OI the truth table for a 2 to 4 line decoder: 15 pts \m Inputs: out out “out Out Enable Inl InO Y3 Y2 Y1 Y0 0 x1x 1 1 1. 1 l O O | l l 1 O ;f 1 0 1|! 1 0 J 1 1 0|; [)1 I. 1 1 llo tl: \ 3) Fill in the table for 0+. Is it rising(+} or falling{—] edge triggered? 10 pts Circle one: Rising edge Or (::> Falling edge Exam2sp11doc CompE 27o NAME: gOLJlﬁLSHS Exam 2 4) Design an up/down BCD counter Mealy Machine with carry/borrow output. The counter must have a carry and borrow output to indicate when it is about to over" or under—flow. The counter should count up when the up/down input = l and count down when the input 2 0. When counting up from state 9, the carry/borrow output should be 2 l, and zero otherwise. When counting down from state 0, the borrow output should be = l. The state values must be the 4 bit BCD values corresponding to decimal 0—9. Draw: {1) the state diagram (10 pts) (2) state table with binary input/state/output values (30 pts) (3) the block diagram (10 pts) of the state machine in the same format shown in problem #1. USe this sheet and the following page. “ﬂag 50 pts total (13 Exam2sp1’l.doc 2 CompE 270 NAME: :ggltj4tﬁr1‘ ) Exam 2 Problem 4, (cont'd) : Exam23p1 1.doc 3 CompE 270 Exam 2 5) For the Moore machine state table shown, fill in the binary state table for the minimum number of flip flops, then fill in the next—state & output truth tables and K—maps (X State is SO, and output is Z), and the minimal SOP equations. 50 pts total State table Current Next State NExt State OutpuEW State I X = o X z 1 Z SO ‘ so 81 0 81 Sl 82 | 1 I_ 32 i s2 33 {p 0 s3 S3 s3 1 Binary Encoded State table Current NExt StateTEEXt State Output Stateszo X=l_|_ Z (70 :90 01 o :91 | 01 _1_o 1:] IOJ: 10 _H :0 {I [L— _1l I Truth tables and K—ma 5: One each for the @State Bit <1;an Truth Tahoe: S Z out bit and one eao tate Bit QO‘"’D‘3 utput 2 Truth Tablgf Truth Tab put Equations: @ DI :2 ea + m-Qo Exam25p1 1.doc NAME: 5E) rt input, Reset CompE 270 NAME: _}:>(¥DATKLSLA<) Exam 2 6)Indicate whether each architecture of the diagrams below represents: an FPGA, PLA, PAL or ROM, Also write the output equations for each output. 5 pts ea Circle 0.:G) Type: FPGA, PLA, or ROM Type: FPGA,QE£5 PAL or ROM Q0 : A4477 g3 Q1 z <) l:> CD _—--...\ Type: FPGA, FLA, PAL or @OMJ Q0 = A0¢QV+©O¢EM @{Qw okatf Q1: ﬂdfg\+ﬂﬂ’gi iggwaQeA €q§».& a5 (SﬂuhCUpeEfuJakﬁf Exam25p11.doc CompE 2'70 NAME: Sbbuﬂ Exam 2 8) Fill in the Q+ and Q’+ table entries: 15 pts R Q s 0’ Complete the timing diagram: 10 pts 9) For the circuit shown, complete the timing diagram: 15 pts 1 > cm W IN \ I / , ; Q__/ @®©@® 10) Draw a four bit adder using Sour labit :ull adders: @pts 1.7, Y’s h v1 Y (<23 </\Co§r Ha, QHCJ G»\ (a; m. Q- S s Exam2\$p11,doc ...
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