270exam2solutions

270exam2solutions - r CompE 270 Digital Systems 510 NAME:...

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Unformatted text preview: r CompE 270 Digital Systems 510 NAME: SOfU Exam #2 - use additional sheets if needed - SHOW WORK for partial credit Red ID#: 1) Draw a block diagram showing a generic Mealy state machine with one input, one output, and the minimum number of D flip flops to implement 5 states. 20 pts 27-14 ?> '5 r———._._ 2) Draw a block diagram showing a generic Moore state machine with one input, one output, and enough D flip flops to implement 3 states using the “one hot” state machine structure. 20 pts 3) Of the two state machines above, circle which type of state machine applies to each of the following statements: 10 pts total, 2 pts ea a) or Moore: May have “false outputs" or “glitches” on its outputs. b) or Moore: Outputs are available earlier than the other type. c) Mealy or Moore: Outputs are a function of state and inputs. (:1) Mealy or Outputs are a function of state only. e)@or @ Setup and hold times must be maintained to guarantee correct 0 eration. ,A {bank p \ -‘ ~—-~ 632$:- ExamZLdoc 1 \ CompE 2'70 NAME: So (U‘QLL‘EJ ) Exam 2 4) A digital radio data receiver has a noisy input signal, but the signal is correct the majority of the time. The signal is sampled 3 times per bit and if there are more ones than zeros, we want to treat it as a one input. Design a Mealy state machine that is a “‘majority vote" detector that indicates when the majority of the last three samples received are ones. When at Clock: 0 l 2 3 4 5 6 7 8 9 A B C D E F In: 0 0 l l l O 0 l 0 l O l l O O 0 Out' 2: X Q l l l 0 0 0 l 0 1 IL 1 O 0 When the first three bits (001 above) are received, at clock time ' but when the next bit is received (fill above) at clock time 3, the output is 1, because two of the three inputs are one (Qil abOVe). Make a block diagram of the state machine, create a state diagram, and deSign the combinational logic to implement the next Exaer.doc 2 CompE 270 Exam 2 Problem 4, continued: be. Q. no 51 1‘ 10 0 00 i Z: Ob+0~C+bL Exam2r.doc 3 CompE 270 NAME: Exam 2 5) For the circuit shown: Flip-Flop Timing Specs: Gate Timing Specs: gynmol nfin Ea) nmx unks Symbol ' gm nmx unfis THGmM) 0 “S 133m 2 <::> HS TPCKQ (delay fi'flm ck to Qout) 3 HS ’T P , Tp MA“ Lani a) Draw the parametric timing 'agram (not functional) showing the input (IN), D, and output (Q) signals, with the timing specifications from above the determine the minimum clock period. ‘+ t 20 pts b) For the circuit and specifications shown, what is the maximum clock frequency that is guaranteed to meet the Specifications? ——mq—_ S 1 1 ——fim 1513:; 3mg + 4,5 + 3n511o is 43m ’ 555' ‘“ Law; pra + T‘PLH + TSU c) What are the setup and hold time requirements for the overall circuit as shown (for input signal IN relative to CK)? 15 Pts 75:0 ale/elk '2 TSu (FF\ 4“ Rm (Cam's) '4 3 + 5|- :@ MILK Tn wmdk : TMFPB #Tp (sag a O -— l 2 4 um _F_ _ hm , i Exam2r.doc CompE 270 NAME: g0 (U ’LfmS Exam 2 6) The outputs of a 2:4 decoder are cennected to the samee numbered inputs of the 4:2 priority encoder. What are the equations for output signals x and y in terms of the input signals a and b? 15 pts 2:4 Decoder 4:2 Priority Encoder Decoder truth table: ' Priority Encoder Truth Table: a lb 310 3/1 3/2 y3 ' i0 il ile3 2: y 0 0 l 0 O O l 0 O O O O O l O l O 0 X l O 0 O l l O O O l O X X l O l O |1 1 0 0 0 1 |x x x |1 1 i1 x = 0. y = b 7 F om the dia ram belo a swer the ue t‘ons: ) r 9 w; n C10 s g. A X9”: ?{‘§fi {AMMng a) Circle the type of device: ‘ “u L_|__ 0:, 4§¥£L& 10 Pts 3. PW Ant); he; on — :— PLA ROM @ BSZC _ ' ' E "'"x r --~x x e +——— B b) Write the equations: _ 1 :;; i A 10 pts x-~* : -~ 3c ~4 uiu BC. I i t t I. "- I I I x = HEC+QE§Q+M§C+ REC --—x - -—--a9 RC —x-x-x r x~* {i}? 0 “an Y Z 'L' IL *___7_._ x -_._,x I__ __g c) Draw the K-map for Y: —-—x—---!- x----x—'—----—\_.\——- -——.- --A£§C\ 15 ptS ' 4.1.: I Tye—L x—1_J»-— 1 NBC x -u x - ix —r—A6C 1 T" A Y x Exam2r.doc 5 ...
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This note was uploaded on 02/26/2012 for the course COMPE 270 taught by Professor Harris during the Spring '08 term at San Diego State.

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270exam2solutions - r CompE 270 Digital Systems 510 NAME:...

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