ch2hwsol - Embedded Controller Design, W00 Problem...

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Embedded Controller Design, W00 Problem Solutions 3 Solutions to Chapter 2 Problems 1. Processors such as the 8031 use multiplexed address/data buses. They require more than one clock cycle to do a memory transfer because some or all of the bus lines are shared. 16 bit addresses alternate with 8 bit data. The ALE (Address Latch Enable) signal indicates when address information (A0-7) is present on the multiplexed address/data bus. The ALE signal is used to latch the least significant 8 bits of the address in an 8-bit register. A minimum of two clock cycles is required to transfer data: one for latching the address when ALE is high, and one for the actual data transfer. How many clock cycles (minimum) would be required if the processor was a 16 bit machine doing a 16 bit transfer? Would the address latch have to be different? The same number would be required of a 16 bit processor (with a 16 bit multiplexed address/data bus). One cycle for address latching, and one for the data transfer. The address latch would have to be a 16 bit latch (or two 8-bit latches) to store the full 16 bit
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This note was uploaded on 02/26/2012 for the course COMPE 475 taught by Professor Staff during the Spring '08 term at San Diego State.

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