Embedded Controller Design, W00
Problem Solutions
4
Solutions to Chapter 3 Problems
For the following problems, refer to the loading example and Figure 315.
1.
A) If a 10K pullup resistor is used, how many additional LSTTL loads can be connected?
B) How many CMOS loads could be added?
When the LSTTL driver's output is 0:
The output is assumed to be at 0.4 volts. This is max V(ol), and represents a noise margin of
0.4 volts from V(il) max of the CMOS and LSTTL loads.
The CMOS gate input is sourcing
a negligible amount of leakage currentless than 1 uA. The LSTTL gate input is sourcing as
much as 360 uA (I(il) max) to the LSTTL output.
The voltage across the 10k resistor is 4.6 volts (Vcc  V(ol) max).
Therefore the current sunk by the LSTTL output is
(4.6/10k) + 360 uA = 820 uA.
The LSTTL output is specified to sink at least 3.2 mA and maintain V(ol) max, so it can sink
an additional 3.2  .820 = 2.38 mA.
Since each additional LSTTL input would source 360 uA, the 2.38mA excess sink capability
of the LSTTL input represents 2.38/0.36 = 6 additional inputs.
When the LSTTL driver's output is 1:
The output is assumed to be at 3.4 volts; the min V(ih) for the CMOS device (3.0v), plus the
same 0.4 volt noise margin that applies to the TTL signals.
This represents a voltage drop of
1.6 volts across the 10k resistor. By Ohm's law, that's a current flow of 160 uA.
The CMOS
gate input is sinking a negligible amount of leakage currentless than 1 uA.
The LSTTL gate input is sinking 60 uA of the 160 available.
The excess source capability is 160  60 = 100 uA.
Since each additional LSTTL input would require 60 uA, the circuit can support only one
more LSTTL input, which is more restrictive than the logic 0 case above.
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 Spring '08
 staff
 Logic gate, LSTTL

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