ch6hwsol - Embedded Controller Design, W00 Problem...

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Embedded Controller Design, W00 Problem Solutions 10 Solutions to Chapter 6 Problems 1. For this problem, use the fastest EPROM program memory from Table 6-2 (the –15 version), the 8031 CPU specs in Table 6-1, and the latch specs from Table 6-3. Ignoring the TCLCL limit on clock speed, how fast can the processor be clocked? Use the connections shown in Figure 6-3, with /PSEN connected to the EPROM /CE pin. First, consider the access time specs. The two access time paths correspond to Paths B and C in Figure 6-3, since path A will always be shorter than path B for the design as shown. For path B, looking at the variable clock entries in Table 6-1: The CPU requires that the data from the EPROM be available TAVIV = 5*TCLCL-100 nS after being presented with a valid address. The -15 version of the EPROM has an address access time of 150 nS max. (EPROM t ACC ). The latch is specified for a maximum D to Q delay, t P D->Q of 16nS worst case. TAVIV = EPROM t
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This note was uploaded on 02/26/2012 for the course COMPE 475 taught by Professor Staff during the Spring '08 term at San Diego State.

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ch6hwsol - Embedded Controller Design, W00 Problem...

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