ch7hwsol - /OUT_CK = /WR * A8 * A7 * A6 * A5 * A4 * A3 * A2...

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Embedded Controller Design, W00 Problem Solutions 12 Solutions to Chapter 7 Problems 1. How many pins would be required on a PLD in order to implement a completely decoded memory and I/O address decoder for the design shown in Figure 7-7? 17 shown plus 8 (A0-7) plus Vcc, Gnd = 27 pins 2. For the problem above, make a revised version of Table 7-1, with the input and output ports mapped to address FFFF hex. Last two lines of table changed to: Address Device selected Data FFFF R/W In/Out port 3. Write the two equations necessary to map the I/O port select signals, /IN_EN and /OUT_CK, of Figure 7-1 to respond only to address FFFF hex. Last two equations changed to add A7. .0 to the I/O port: /IN_EN = /RD * … A8 * A7 * A6 * A5 * A4 * A3 * A2 * A1 * A0
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Unformatted text preview: /OUT_CK = /WR * A8 * A7 * A6 * A5 * A4 * A3 * A2 * A1 * A0 4. If a PROM is used to implement the PLD function above, how many memory bits would be desired? How many fuses would be required of a PAL style version, using the PAL shown in Figure 7-6? PROM: (AND array fixed, OR array has fuses, the memory bits) 16 addresses plus /PSEN, /RD, /WR is 19 input (address) lines and 6 outputs (assuming you can find a six bit wide memory!) Total bits = 2^19 * 6 = ~3M bits! PAL: (AND array has fuses, OR array is fixed) 2 fuses per input (true and complement) And one AND gate per product term 19 inputs * 2(fuses per input) * 4 product terms Total fuses = 19*2*4 = 152...
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This note was uploaded on 02/26/2012 for the course COMPE 475 taught by Professor Staff during the Spring '08 term at San Diego State.

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