Compe475_T1_Fa10_Sol

Compe475_T1_Fa10_Sol - CompE 475 Mid-term 1 Fa10 x0404L...

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CompE 475 Mid-term 1 Fa10 x 040 4L Solutions Part 1 - closed book/notes Definitions: 2 Points Each: Define the terms. 1) tsu Setup Time is the time an input must be valid and stable prior to the active clock edge. 2) Read Mostly Memory is non-volatile memory that is most often read, and less frequently written to, such as Flash or EEPROM. 3) RAM (Random Access Memory) is organized in rows and columns, so that any location can be accessed in the same amount of time. 4) The logic threshold (Vt) is the voltage which defines the decision point for a logic input to distinguish between logic one and logic zero. This can vary over time, voltage, and from gate to gate. It is only guaranteed to stay in the region between Vih(min) and Vil(max). 5) Memory Refresh is a charge replenishment process that is required only for DRAM memories to replace the charge that leaks off the capacitor. 6) Metastability refers to the invalid state that a clocked device, such as a flip-flop, may enter when the setup/hold time is violated (fig 3-5). 7) DRAM is a type of read-write semiconductor memory that stores bits as charge (or absence of charge) on a capacitor or gate of a MOSFET transistor. The charge leaks away so it must be periodically refreshed. 8) Multiplexed Address is used to carry time-multiplexed portions of a DRAM’s address input bits on the same bus by row and column, one at a time, reducing the number of pins. De-multiplexing of the address and data is done using RAS- and CAS- control line like ALE and a latch. 9) Bus contention is when more than one tri-state driver output is enabled to drive the same line(s) in opposite states at the same time, potentially causing high currents to flow, glitches, EMI, etc. 10) EEPROM Electrically Eraseable Programmable Read Only Memory, uses Fowler-Nordheim electron tunneling to store data as charge on a floating gate. Slow (~uS-mS) to erase/program. Can be erased and programmed one byte at a time. Limited (1K to 1M) erase-write cycles to wear out. Test 1 11) What are the nominal noise margins using the data sheets you have been provided with for the XOR gates and flip-flops? 15 pts NOTE: For all the conditions below, there is only one load , so Iol and Ioh are limited to one load’s input current, which is 1uA max for FF and 5uA for gate => so all Io’s << 100 uA . using XOR gates driving XOR gates both Vcc = 3.3V:
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Compe475_T1_Fa10_Sol - CompE 475 Mid-term 1 Fa10 x0404L...

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