475sample2 - CompE 475 Mid-term exam samples T2xECD041 1...

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CompE 475 Mid-term exam samples T2xECD 041 1 1) When two devices bus drivers, such as a processor and a memory device data bus outputs have short periods of bus contention because the memory output drives the bus too long at the end of a read cycle, what are two design options that will correct the problem? 10 pts 2) When evaluating the timing specifications, the I.C. specification sheets list the test output loading conditions under which the chip is specified to operate. (e.g. RL = XX Ohms, CL = YY pF) What can you do when they're exceeded? (Answer for both R < RL and C > CL) 10 pts 3) Which type of address latch is preferred (for timing purposes) to latch the address on the 8031 multiplexed address and data bus: edge triggered D F-F (e.g. '374) or transparent latch (e.g. '373)? 10 pts Why?
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CompE 475 Mid-term exam samples T2xECD 041 2 4) Each of these memories store data as a charge. Describe how erasure and programming is different from the others for each type of memory. 15 pts
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475sample2 - CompE 475 Mid-term exam samples T2xECD041 1...

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