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475sample2solutions - CompE 475 Mid-term exam samples...

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CompE 475 Mid-term exam samples T2xECD 041 SOLUTIONS 1 1) When two devices bus drivers, such as a processor and a memory device data bus outputs have short periods of bus contention because the memory output drives the bus too long at the end of a read cycle, what are two design options that will correct the problem? 10 pts There are two practical solutions to bus contention: 1) Buy an I.C. that has a faster output disable time Tod, or 2) Add a tri- state buffer to the data bus of the memory which has a slow output disable time, since tri-state buffers have a faster output disable time. In some cases, such as the 8031, slowing the clock may also work. Wait states won't help! Slowing the clock doesn't always work. 2) When evaluating the timing specifications, the I.C. specification sheets list the test output loading conditions under which the chip is specified to operate. (e.g. RL = XX Ohms, CL = YY pF) What can you do when they're exceeded? (Answer for both R < RL and C > CL) 10 pts Generally, if the driver is overloaded from either an AC (C>CL)
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475sample2solutions - CompE 475 Mid-term exam samples...

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