475SampleT2b - CompE 475 Sample Test 2 Fa10xECD974 1) When...

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CompE 475 Sample Test 2 Fa10xECD974 1 1) When two devices, such as a processor and a memory device have short periods of bus contention because the memory output drives the bus too long at the end of a read cycle, list at least two design options that will correct the problem? 2) When evaluating the timing specifications, the I.C. specification sheets list the test ouput loading conditions under which the chip is specified to operate. (e.g. C L = YY pF) What can you do when they're exceeded? (i.e. when the actual load C L > C L specified) 3) Which type of address latch is preferred (for timing purposes) to latch the address on a multiplexed address and data bus: an edge triggered D F-F (e.g. '374) or transparent latch (e.g. '373)? Why? 4) For a fixed clock rate, determine what the memory specs need to be for the following system. Refer to the 8031 timing specs (use Tables 6-1, 6-6 of the text). The clock frequency is 10 MHz . What are the maximum enable and address access time requirements for the program and data
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This note was uploaded on 02/26/2012 for the course COMPE 475 taught by Professor Staff during the Spring '08 term at San Diego State.

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475SampleT2b - CompE 475 Sample Test 2 Fa10xECD974 1) When...

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