475SampleT2bsol (2)

475SampleT2bsol(2) - CompE 475 Sample Test 2 Fa10xECD974 Test 2 1 When two devices such as a processor and a memory device have short periods of

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CompE 475 Sample Test 2 Fa10xECD974 Test 2 1) When two devices, such as a processor and a memory device have short periods of bus contention because the memory output drives the bus too long at the end of a read cycle, what are two design options that will correct the problem? There are two practical solutions to bus contention: 1) Use a different I.C. that has a faster output disable time Tod , or 2) Add a tri-state buffer to the data bus of the memory which has a slow output disable time, since tri-state buffers have a faster output disable time. Wait/stretch cycles won't help! Slowing the clock usually doesn't work either. 2) When evaluating the timing specifications, the I.C. specification sheets list the test output loading conditions under which the chip is specified to operate. (e.g. R L = XX Ohms, C L = YY pF) What can you do when they're exceeded? (Answer for both R < R L and C > C L ) Generally, if the driver is overloaded from either an AC (C>CL) or DC (R<RL) point of view, the simplest solution is to select a driver with higher output drive current . It is also possible to parallel outputs of the same type FROM THE SAME DEVICE to get higher output drive for excessive DC or AC loading. For signals which are overloaded in terms of their AC load only, the output timing specs can be derated to compensate for the resulting slower output voltage slew rate (longer rise and fall times). Sometimes loads can also be split (e.g. buses) and driven by multiple outputs separately.
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This note was uploaded on 02/26/2012 for the course COMPE 475 taught by Professor Staff during the Spring '08 term at San Diego State.

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475SampleT2bsol(2) - CompE 475 Sample Test 2 Fa10xECD974 Test 2 1 When two devices such as a processor and a memory device have short periods of

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