CompE475samples3x270T3-F11

CompE475samples3x270T3-F11 - CompE 475 sample problems 3 1)...

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CompE 475 sample problems 3 1 1) Metastability may be caused by a violation of what specification(s)? 10 pts 2) Fill in the truth tables and the equation for the circuits below: D A B C A B C D 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Write the logic equations: D = __________ D = __________ F = __________ 10 pts 10 pts 5 pts ABCD 000 001 010 011 100 101 110 111 A B F 0 0 0 1 1 0 1 1
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CompE475samples3x270T3-F11.doc 2 3) From the specs from the Data Sheets on the next pages what is the noise margin for each of the combinations below? (Vcc=5v) 2 pts ea Gate Gate Noise Margin Output Input Logic Zero Logic One Type Æ Type A B __________ ___________ B A __________ ___________ C B __________ ___________ D A __________ ___________ C A __________ ___________ 4) For the circuit and specifications shown, find the parameters in a) & b): Using specs for the 2 input gate, inverter and Flip-flop 2: a) What is the minimum clock period for the circuit shown above? 15 pts
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CompE475samples3x270T3-F11 - CompE 475 sample problems 3 1)...

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