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Altera_DDC_HTML - Designing Digital Down Conversion Systems...

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Unformatted text preview: Designing Digital Down Conversion Systems using CIC and FIR Filters 11/23/07 9:50 AM Literature Licensing Buy On - Line Download Entire Site Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On - Line Knowledge Database | Devices | Design Software | Intellectual Property | Design Examples | mySupport | Reference Designs Products MAX/MAX II Stratix/Stratix GX Nios II Functionality Arithmetic Memory Bus & I/O Logic Interfaces & Peripherals DSP Communications PLL & Clocking Design Entry Quartus II Project Tcl VHDL Verilog HDL C Code Examples DSP Builder TimeQuest Home > Support > Design Examples > DSP Builder > Designing Digital Down Conversion Systems using CIC and FIR Filters Print This Page E - mail This Page Designing Digital Down Conversion Systems using CIC and FIR Filters The Designing Digital Down Conversion Systems design example, featuring Altera ® CIC and FIR MegaCore ® , demonstrates a multichannel, multirate digital system using Altera's DSP MegaCore intellectual property (IP). Sample rate conversion has a wide range of applications in modern digital systems, especially wireless communications systems such as WCDMA and WiMAX systems. Efficient implementation of decimation and interpolation can be accomplished by concatenating cascaded -integrator-comb (CIC) and finite impulse response (FIR) filters. In this example we demonstrate a data rate down conversion system that can be commonly seen in time division multiplexing (TDM) WiMAX receivers. The overall system diagram is shown in Figure 1. For more details about Altera wireless digital up/down solutions please refer to Application Note 421 Accelerating WiMAX DDC & DDC System Designs (PDF). Figure 1. TDM Digital Down Conversion System Block Diagram Simulation Tools Mentor Graphics ModelSim Cadence NCsim Synopsys VCS Legacy Examples Graphic Editor AHDL Model The input to the design example is from two independent data sources, such as the inphase (I) and quadrature (Q) components of a digital communications system. The inphase signal is a sine wave with a center frequency of 4.57 MHz. The quadrature signal is a cosine wave also centered at 4.57 MHz. The combined, time multiplexed input data stream is sampled at 182.784 MHz, so the corresponding data rate for the inphase and quadrature signals is 91.392 MHz. Part of the input signal is corrupted by high-frequency additive noise. The CIC and FIR filters convert inphase and quadrature signals sample rate to 11.484 MHz while maintaining the input signals spectrum information. The decimation filters also reject out-of -band noise. Therefore, the output of this rate conversion system should be noiseless down sampled sinusoidal waves of frequency 4.57 MHz. For well defined rate change systems, the narrow band information signal should maintain its spectrum from input to output, as demonstrated in this design example. Features Decimation or interpolation is implemented efficiently using the Altera CIC Compiler MegaCore. Altera's FIR Compiler is configured to have an inverse sinc frequency response to compensate CIC filter droop. A MATLAB script designing CIC compensating filter is provided for your reference. The script uses the frequency sampling method to design a FIR filter that has an inverse sinc frequency response. The overall system response is plotted for you to verify key system specifications such as the pass -band ripple and stop-band attenuation. Multiple input data sources are supported. For wireless/wire line applications input data can be viewed as time division multiplexed. For other applications, data sources can be viewed as interleaved. Altera's Packet Format Converter is included to properly de -interleave multiple data sources for display. Altera's Avalon® Streaming Interface is used to transfer packet data from multiple data sources between MegaCores. For more information about Avalon Stream Interface, please refer to the Avalon Streaming http://www.altera.com/support/examples/dsp-builder/exm-digital-down-conv-cic-fir.html Page 1 of 3 Designing Digital Down Conversion Systems using CIC and FIR Filters 11/23/07 9:50 AM Interface Specification (PDF). Files Download the files used in this example: Download Download Download Download DDC Example Design File (Version 71) DDC Example README File (Version 71) DDC Example Design File (Version 61) DDC Example README File (Version 61) Files in the zip download include: TDMDDC.mdl - DSP Builder design file ciccomp.m - MATLAB script for designing an inverse sinc CIC compensation filter cic.vhd - wrapper file to generate the Altera CIC Compiler IP core fir.vhd - wrapper file to generate the Altera FIR Compiler IP core fdcoeffR4N8M1L110.txt - pre -generated compensating FIR filter coefficients Parameters Figure 2 shows the top-level diagram of the CIC and compensation FIR design example in DSP Builder. Figure 2. CIC and compensation FIR design example in DPB Builder View Full Size The overall frequency response specifications are given in Table 1. Based on the frequency response requirement, parameters for CIC and FIR filters are selected and are given in Table 2 and Table 3. Table 1. WiMAX DDC Example Total Spectrum Requirement Parameters Value Input Sampling Frequency 91.392 MHz Output Sampling Frequency 11.424 MHz Pass -Band Edge 4.75 MHz Pass -Band Ripple < 0.05 dB Stop-Band Attenuation > 90 dB Table 2. Parameters for CIC Filter CIC Parameters Filter Type Value Decimation Number of Stages 8 Rate Change Factor 4 http://www.altera.com/support/examples/dsp-builder/exm-digital-down-conv-cic-fir.html Page 2 of 3 Designing Digital Down Conversion Systems using CIC and FIR Filters 11/23/07 9:50 AM Differential Delay 1 Number of Interfaces 1 Number of Channels Per Interface 2 Input Data Width 8 Output Data Width 16 Hogenauer Pruning On Output Rounding Convergent Table 3. Parameters for FIR Filter FIR Parameters Value Rate Specification Decimation by 2 Input Channels 2 Input Bitwidth Signed binary 16 Output Bitwidth Full resolution Coefficient Scaling None Stratix ® II Device Family Structure MCV Pipeline Level 2 Clocks per Output Data 2 Data Storage M4K Coefficient Storage M512 Multiplier DSP blocks Coefficients Input From file Related Links For more information on related features used in this design example in your project, go to: DSP Builder DSP Builder User Guide (PDF) DSP Builder Reference Manual (PDF) WiMAX DUC DDC Reference Design Webpage AN 421: Accelerating WiMAX DUC & DDC System Design (PDF) CIC Compiler User Guide (PDF) FIR Compiler User Guide (PDF) Please Give Us Feedback Sign Up for E - mail Updates Rate This Page Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On- Line Knowledge Database | Devices | Design Software | Intellectual Property | Design Examples | mySupport | Reference Designs Contact Us | Site Help | Site Map | Privacy | Legal Notice Copyright © 1995 - 2007 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation http://www.altera.com/support/examples/dsp-builder/exm-digital-down-conv-cic-fir.html Page 3 of 3 ...
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