Cadence_Verilog - EE4702 Informal Cadence Verilog...

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Unformatted text preview: EE4702 Informal Cadence Verilog Simulation Guide Bryan Audiffred February 19, 2004 1 Introduction This brief guide should get you up and running with the Cadence Verilog simulator. It is by no means comprehensive. Please refer to the Cadence documentation for the exhaustive information. Part of being a good engineer is sifting through mountains of unreadable datasheets , . I can help you with getting started and performing the operations needed to succeed in the class, but please refer to the documentation first. 2 Goals After reading this guide you should be able to: 1. Compile Verilog source 2. Simulate Verilog source 3. Interact with and debug a Verilog simulation 4. Analyze waveforms with SimVision 3 Setup We will be using the following cadence tools for Verilog simulation, the NC- Verilog Compiler, SimVision interactive simulator, and SimVision Waves waveform viewer. Don’t worry too much about the product names as they change every release cycle. All of the cadence software is located in the path /opt/local/cadence . The simulation tools are located in /opt/local/cadence/LDV34 , and the documentation is in the ./doc direc- tory. A nifty documentation viewer is available by executing “cdsdoc”. 1 All paths are now automatically set when you log on, so you should be able to execute all tools without trouble. 4 Creating Source Code Verilog source is simply a text file. It goes without saying, but NC-Verilog will not read in formatted Microsoft Word documents. The standard text editor in the CDE dock will be dtpad. You may launch it from the dock or from the command line. Be aware that moving text documents from windows or mac may introduce undesired effects. You can use the dos2unix command if you would like to convert a windows text file to unix ASCII encoding. You may of course use any editor you wish, no doubt most of you will....
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This note was uploaded on 02/26/2012 for the course EE 3755 taught by Professor Staff during the Fall '02 term at LSU.

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Cadence_Verilog - EE4702 Informal Cadence Verilog...

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