Notes8

Notes8 - LSU EE 3755 Computer Organization Verilog Notes 8...

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/// LSU EE 3755 Computer Organization // // // /// Contents // Event Control (@) // Syntax and Simulation of if else // Syntax and Simulation of case // Syntax and Simulation of for, while, repeat,forever // Ripple Adder: Combinational v. Sequential // Miscellaneous Examples /// References // // :P: Palnitkar, "Verilog HDL" // :Q: Qualis, "Verilog HDL Quick Reference Card Revision 1.0" ////////////////////////////////////////////////////////////////////////////////
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/// Event Control (@) // :P: 7.3.2 // An /event control/ statement pauses the execution of // the procedural code in which it appears // until the specified event occurs. // The general use of event control statements will be briefly // described here. // :Syntax: @( EXPR ) STATEMENT; // // Evaluate EXPR and resume execution starting with STATEMENT when // value of EXPR changes. // :Syntax: @( EXPR1 or EXPR2 or. .. ) STATEMENT; // // Evaluate EXPR1, EXPR2, . .. and resume execution starting with // STATEMENT when the value of any of the EXPR change. // :Syntax: @( posedge EXPR ) STATEMENT; // // Resume execution starting with STATEMENT when EXPR changes from // 0 to anything or from anything to 1. // :Syntax: @( negedge EXPR ) STATEMENT;
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// // Resume execution starting with STATEMENT when EXPR changes from // anything to 0 or from 1 to anything. // :Syntax: @( EDGE1 EXPR1 or EDGE1 EXPR2 or . .. ) STATEMENT; // // EDGE1 can be posedge, negedge, or nothing. // Resume execution at STATEMENT when any of the EXPR change to // the specified value (nothing, which means just EXPRx, // means any change, @(EXPR) Statement;). // // The event controls can be used anywhere a statement can go. In // practice they are almost always used right after "always @," // which is the way they will be covered in the following // sections. //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// /// Syntax and Simulation of if else // :P: 7.4 // Similar to C language.
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// :Syntax: if( EXPR ) STATEMENT; // // If EXPR evaluates to a non-zero number, execute STATEMENT. // Note that STATEMENT could be a begin/end block. // // :Syntax: if( EXPR ) STATEMENT1; else STATEMENT2 // // If EXPR evaluates to a non-zero number, execute STATEMENT1 // otherwise execute STATEMENT2. // :Example: // // Examples of if/else. // Doing nothing useful. // Focus on usage of if statement. . module if_examples(); integer a, b, c, d, x; initial begin if( a < b ) c = 1;
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if( a < b ) c = 2; else d = 3; // Note: x = 5 is always executed; c = 3 only if a < b. // This is an example of bad style, x = 5 should be put on
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Notes8 - LSU EE 3755 Computer Organization Verilog Notes 8...

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