verilog_hw012005

verilog_hw012005 - EE 3755 Homework 2 Due TBA Estimated...

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EE 3755 Homework 2 Due: TBA Estimated time to solve: Prob.1 60 mins.// fill out the program file, leave Prob.2 60 mins.// on your directory and submit Prob.3 60 mins.// a hard copy. Total: . How to submit? // Hard copy at the class room. It should contain the output. ######################################################### ###Use “ script “ command to take a snapshot of your program. ###After run “script “ ###Use “ cat ” command to display contents of your program. ###Use “ncverilog ” to run your program. ###then stop the script. ### if you want to know more about “script” then type “ man script ” at the shell ############################################################# For Problem 1,2,and 3 you also have to leave your program on your account. //Program – problem 1,2, and 3. Make a HW folder and Copy the homework template into your account and name it hw1.v. Simulate the welcome module in the homework template. The logic diagram below is a 1-bit slice of a circuit that is used to determine whether a=~b. One bit of one integer is put on input a and one bit of the other integer is put on input b. (If the number has ten bits then ten slices would be needed.)
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verilog_hw012005 - EE 3755 Homework 2 Due TBA Estimated...

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