lec11_mem - Announcement CSE120 Principles of Operating...

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1 CSE120 Principles of Operating Systems Prof Yuanyuan (YY) Zhou Lecture 11: paging May 11th, 2011 Announcement Wednesday, May 25 th , Teradata guest lecture (2 speakers) June 1st, Wednesday, Android TBD (maybe): guest lecture from Intel (Product management) Final exam review will be done in discussion section Don’t forget about project 2! Don’t forget about course review Give your feedback (both good and bad ) 5/11/2011 CSE 120 2 Review Page How is different from variable size partition? How is different from segmentation? How is virtual address to physical address translated? Why is page size always a power of 2? For a 32 bit address, if the page size is 4KB, how many bits are used as the virtual page number? How many virtual pages can a process have? Does an instruction use virtual address or physical address? 5/11/2011 CSE 120 3 Review Page table What is a page table? Does each process have a page table? What is stored in each entry of a page table? Two level page table What is a two level page table? Why is it introduced? For what purpose? Why can it serve this purpose? For a system with 4KB as the page size, the master page table fits into one page, each pointer & mapping is 4Bytes, how many entries for each secondary page table? 5/11/2011 CSE 120 4
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2 Review TLB What is TLB? What is it for? Is it implemented in hardware or it is an OS data structure? Why does it work? Usually how big is it? What is a TLB hit rate? Why is it important? What is a TLB miss? How is it handled? What are the trade-offs between different approaches? 5/11/2011 CSE 120 5 Agenda for this lecture Context switch Demand paging Put things together TLB miss, page fault, etc Some optimizations leveraging VM 5/11/2011 CSE 120 6 What happen at a context switch? Each process has its own virtual address from 0 to 0xFFFFFFFF (if 32 bits) Mapping is for EACH process So what happen at a context switch (from process 1 to process 2)? Before the switch, TLB holds the mapping for process 1? Will Process 2 be able to use these mapping? If not, what we should do? TLB flushing: invalidate all TLB entries! Next few memory accesses by process 2 will have to suffer from TLB misses----expensive! 5/11/2011 CSE 120 7 5/11/2011 CSE 120 8 Paged Virtual Memory We’ve mentioned before that pages can be moved between memory and disk This process is called demand paging OS uses main memory as a page cache of all the data allocated by processes in the system Initially, pages are allocated from memory When memory fills up, allocating a page in memory requires some other page to be evicted from memory
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This note was uploaded on 02/26/2012 for the course CSE 120 taught by Professor Staff during the Spring '08 term at UCSD.

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lec11_mem - Announcement CSE120 Principles of Operating...

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