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HW2_Key

# HW2_Key - Homework#2 Problems Points 100 Reading Sections...

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Homework #2: Problems Points: 100. Reading: Sections 1.3-1.4, 2 (skim), 3.1 HW2-1. Answer the following 4 questions (parts 1-4; 5 points each): Part 1. For each of the following bit patterns, identify the integer value that would be encoded into this bit pattern using the 8- bit 2’s complement representation: a. 00100111 = 39 b. 00011011 = 27 c. 10001110 = -114 d. 10101100 = -84 e. 11111111 = -1 Part 2. Construct a Huffman code using the frequencies presented for each of the letters given below. In presenting your answer, just show the encodings, not the tree. Assume that the subtree of lesser frequency should be placed on the left side. Also, observe the convention that places 1s on the left branches and 0s on the right branches. Letters: { A, D, E, J, M, S, T, Y } Frequencies, respectively: {.0781, .0411, .1305, .0023, .0262, .0646, .0902, .0151} ENCODING SCHEME: A = 000 D = 111 E = 01 J = 11011 M = 1100 S = 001 T = 10 Y = 11010 Part 3. For each of the following codes, give the Hamming distance of the code: a. { 1101, 1010, 0101, 1110 } = 1 b. { 11100, 10011, 10110, 11101, 11111 } = 1 c. { 11011, 10101, 11111, 00000, 10110 } = 1

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Part 4. For each of the following codes, add a parity bit to the code. The parity bit should be the leftmost bit in each of the encodings and should be used to ensure that each encoding has even parity. a. {100, 011, 001, 111 } -> parity add order 1, 0, 1, 1 b. { 1110, 0010, 1010, 1000, 0110 } -> parity add order 1, 1, 0, 1, 0 c. { 01001, 11100, 11001, 00000, 10111, 10010 } -> same 0, 1, 1, 0, 0, 0 HW2-2. (5 points each ) Assume that a computer’s address bus is 14 bits wide. a. How many memory locations can the computer have? 2^14 16,384 b. If the memory system is byte addressable, how many bytes of memory can it have? 2^14*1 16,384 c. How many bytes of memory can the system have if it is exactly 32-bit addressable? 2^14 addresses * 4 bytes at each address = 2^16 = 65,536 HW2-3. For the following questions, refer to the figure given below (similar to Figure 3.8 on page 81 of the book) and assume that the memory system is aligned and 2-byte addressable, with a 14-bit address bus (unless stated otherwise).
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