ECE150_2008FALL_EXAM2__[0]

# ECE150_2008FALL_EXAM2__[0] - ECE 150 Digital Logic Design...

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Unformatted text preview: ECE 150 Digital Logic Design Fall 2008 Final Exam Name: ________________________________________ Email: ________________________________________ Write all of your answers directly in this test booklet. Use the backs of pages if necessary. Feel free to use scrap paper, but do not hand it in. Please also write your name on the top of each page. Question 1: Counters (a) Using four positive edge-triggered J-K flip-flops, draw a logic diagram for a 4-bit, synchronous, binary counter. (b) Label the flip-flops in your diagram above. Without considering propagation delays, draw a timing diagram that compares the clock signal to the outputs of each flip-flop from part (a). (c) In class, we have discussed the following logic diagram for a 3-bit, up/down, binary, synchronous counter: Write a Boolean expression representing the input to the clock of FF2. (d) Express in English the meaning of the Boolean expression from part (c). Explain why this is appropriate to control the clock input of this flip-flop.this is appropriate to control the clock input of this flip-flop....
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## ECE150_2008FALL_EXAM2__[0] - ECE 150 Digital Logic Design...

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