ECE150_2008SPRING_PROJ1__[0]

ECE150_2008SPRING_PROJ1__[0] - The Cooper Union for Union...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: The Cooper Union for Union for the Advancement of Art and Art Art The Cooper Union for the Advancement of Science Fall 2007 SPRING 2007 Fall 2007 2008 The Cooper the Advancement of Science and Science and Fall Digital Logic Design: ECE150: Prof. Risbud Prof.Union for the AdvancementHARDWARE DESIGN DESIGN Digital Logic Design: Advancement of Digital Logic Design:The Cooper Risbud ECE150: The Cooper Union for the ECE150: Prof. Risbud Science and Art HARDWARE DESIGN ASSIGNMENT #1 ASSIGNMENT #1 Fall 2007 Fall HARDWARE 2007 of Science and ArtASSIGNMENT #1 DUE THU. 11/01 (starting (starting 5team size =team = 2 = 2 DUE THU. 11/01 (starting @ @ 5 PM): 2 size DUE THU. 11/01 @ 5 PM): PM): team size 3/6 DUE THU. 11/01 (starting @ 5 PM): team size = 2 5 PM): team size = 2 DUE THU. 11/01 (starting @ Hardware DesignDesign Assignment #1: #1: Braille Hardware Assignment #1: BrailleBraille Hardware Design Assignment Hardware Design Assignmentwhich visuallyaAssignment #1: person to assess #1: Braille Braille isBraille is a system aBraille is a system which allows a visually challenged person to assess system Hardware a allows challenged person to assess which allows Design visually challenged Braille Digital Logic Design: ECE150: Prof. Risbud HARDWARE DESIGN ASSIGNMENT #1 Digital Logic Design: ECE150: Prof. Risbud HARDWARE DESIGN ASSIGNMENT #1 alphanumerics by feeling allows a visually challengeddots. dots.assessshall we shallwe shall assess Braille isalphanumerics by feeling a pattern of raised this exercise,In this challenged person to aalphanumerics byBraille isaapattern of raised In to visually exercise, system which a pattern of raised dots.which allowsthis exercise, feeling system In person a we deal withdeal digitsthethe sopatternsothat only thatfeelingonly theDecimal Coded Decimal the with only, a assumeof raised by only theexercise,Coded dots. In alphanumerics by feeling digits only,assumedots.BinaryaCoded Binary Decimal this exercise, we shall deal with digits only, so assume In this Binary we shall alphanumerics the that pattern of raised (BCD) numbers numbers sothroughwith the digitsBinaryso You are that only to design design Decimal deal with(BCD) 0 through 9assume 9 will to your circuit.toassume to design the Binary Coded the digitsnumbers will be that 9 will be only, Coded Decimalare (BCD) only, 0 0deal input be inputinput circuit. You You are to through only the to your your circuit. and buildand buildthrough 9which convertsBrailleto Braille will areon the to your table below.are to design aand buildcircuit will be input yourthrough 9You table below. the circuit. circuit a a circuit(BCD) numbers 0 circuit. Braille input on (BCD) numbers 0 which converts BCD totoBCDBCD toon based based table below. You which converts based the be to design and build a circuit which converts build a circuit which converts BCD to Braille based on the table below. and BCD to Braille based on the table below. Table of Table toof BCDcorrespondence for the BCDthe BCDthrough through 9: (The 9: (The assumption BCD of Braille to Braille correspondence digits 0 BCD digits 0 through assumption Table BCD to Braille correspondence for for the digits 0 9: (The assumption is that some that some electromechanicalfor the BCDcorrespondence forfor isBCD digits 0 through 9: (The assumption device device raises that dot a dot the assumption Table of is that to Braille correspondence device exists raises0athrougheach LED that is on.) is on.) BCD some electromechanicalBCDthatBraillea digits raises LED9: (The on.)LED that is electromechanicalTable ofexists toexists thatdot for each for that each is that some electromechanicalisdevice exists that raises a dot for eachexists that raises a dot for each LED that is on.) that some electromechanical0device 0 LED 0 is on.) 1 1 0 DATA DATA A D 0 0B A 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 DCB 0C 0 0 0 0 0 1 10 1 DATA DCBA 0000 0001 0010 0011 INPUTS INPUTS (###) (zero) (zero) (three) (four) (three) (five) (four) INPUTS 0 (###) 0(one)1 0(two)0 (one)(two)(two)0 0 (three)1 (###) 0 0 (zero) (one) 0 0 1 1 0 1 DATA DCBA 000 DATA0 1 D C B A 0 0 0 0 0 1 0 1 000 INPUTS (###) (zero) (one) (two) (###) (three) (four) INPUTS (zero) (five) (one) W X X BRAILLE BRAILLE BRAILLE W W X PATTERN PATTERN Y Z W X BRAILLE PATTERN Y YZ Z BRAILLE W X PATTERN PATTERN Y Z Y Z 0100 (six) (five) (four) 0110 0010 (six) (two) 0101 0110 0111 1000 1001 (seven) (eight) ) (nine) ) (nine) (six) (seven ( (eight) (six) (nine) 0(five) 1 0 0 0 1 0seven 0 1(eight)0 1 1 1 1 0 0 0 01 1 1 0 1 0 0 0 10 1 011 01 10 ((three) (eight) (nine) seven) (four) (five) (six) (seven) (eight) 1001 (nine) WORK IN PAIRSIN PAIRS AND DESIGN CAREFULLY: WORK INAND DESIGNDESIGN CAREFULLY: WORK PAIRS AND CAREFULLY: Use DIP switches AND DESIGN CAREFULLY: C, DESIGN A. WORK INUse DIP switches tothe provide the B & A. D, C, A. & CAREFULLY: PAIRS to provideWORK IND, C, inputs Use DIP switches provide the inputs AND B & B to inputs PAIRS D, The LEDsThe LEDsprovide the inputs switches& A. is a the .inputs D,.a B & A. must light must light DIP corresponding variable is a corresponding variable Use DIP The LEDs must light Usewhen D, C, B to provide variable is C, . switches to when thewhen the the corresponding The LEDsThe LEDs when theThe patterns as seen in the as incorresponding variable is a The LEDsoriented be the LEDs in patterns whenboxesthein the boxes above. must be must be in orientedthe thelight as seen seen boxes above. light must oriented in must variable is athe . above. corresponding patterns . You LEDsonlymay the six basic sixpatterns asgatesNAND, NOR, NAND, XOR).& XOR). XOR). basic must (AND, OR, OR, NOT The mayYou use only use thethe six(AND, OR, oriented in the patterns as seen NOT & must be oriented in gates basic be (AND, NAND, NOR, NOT You may only use The LEDs gatesseen in the boxes above. & NOR, in the boxes above. You have onlyhave the six basic supplyyour design must basic gates (AND,withinthe following NOT &following a limited supply of parts, so(AND, so your six fitNOR, fit within OR, NAND,of the following mayYou use a limited supplymayof parts, so your designNOT & XOR).of eachof each of the XOR). gates parts, OR,the designwithinmustof each of one NOR, You have a limited You of only use NAND, must one fit one types: quad limited supplyinput AND,OR, NAND, must fitXORINVERTER of the following one of each of the following types: quad dual of NAND, NAND, OR, OR, NOR, and hex INVERTER fit within You have types: input AND,input AND, limitedXOR and hex XORyoureach INVERTER a dual quad dual parts,have a NOR, supply ofwithin so and design must You so your design NOR, parts, one of hex Circuits thatdual designed designed and/or constructed poorly will beOR,be penalized. hex INVERTER Circuits that AND, NAND,quad dualconstructed poorly will NOR, types: quad are inputare and/or constructed poorly will behex INVERTER XOR and Circuits that are designed OR, NOR, XOR and NAND, penalized. types: and/or input AND, penalized. Circuits that are designed and/or constructed poorly willand/or constructed poorly will be penalized. Circuits that are designed be penalized. DOCUMENTATION & NOTES:NOTES: DOCUMENTATION & & NOTES: DOCUMENTATION You must You8.5" x use paper x 11" paper for all of NOTES: You must use 8.5" DOCUMENTATION & documentation. use must & 8.5"11" all of your documentation. x for DOCUMENTATION11"NOTES: paper for all of youryour documentation. You must You8.5"the11" paperYouKarnaugh8.5" xthe followingpart ofas partas part of your documentation. You must x include the all of use following paperas page page documentation. include include the Karnaughyour maps11" the following your of your documentation. use must Karnaugh maps on the documentation. for all for must maps on on page You must You must provide You must include the Karnaugh maps of yourfollowing page as part of your documentation. You mustthe explanation explanation of "non-standard"reductions/minimizations. provide an Karnaugh maps on"non-standard"page as part on boolean reductions/minimizations. explanation of any any boolean boolean reductions/minimizations. include provide an an of any the following"non-standard" the documentation. You must You mustlogic, boardlogic, board and schematic (circuit) "non-standard" boolean reductions/minimizations. You mustaprovide a logic,must provide(circuit) diagramof any diagram design. design. design. provide an provide You board and schematic boolean reductions/minimizations. your explanationandany "non-standard" (circuit) to support your to support a of schematic an explanation diagram to support your You must You mustbulleted list bulletedprovide(circuit)or problems that you(circuit) diagram to support your design. You mustaprovideboard of must listissues logic, diagram to schematic encountered. provide logic, a bulletedschematic issuesthat you and support your design. provide You issues of problemsproblems encountered. a and list or of a or board that you encountered. You must provide a bulleted list of must provide a bulleted you of issues or problems that you encountered. You issues or problems that list encountered. Block diagram of the systemthe system you willdesigning and constructing Block diagram ofof you willyoudesigning and constructing constructing Block diagram the system be will be be designing and Block diagram of the system youdiagram of the system constructing Block will be designing and you will be designing and constructing D C D B C A B A D D C C B B A A W W W X X X Conversion D Conversion Conversion W Y Conversion Y Y Circuit Circuit X Conversion Circuit C Z Z Y Circuit B CircuitZ Z A W X Y Z The Cooper Union for Union for the Advancement of Art and Art Art The Cooper Union for the Advancement of Science Fall 2007 2007 2007 Fall The Cooper the Advancement of Science and Science and Fall Digital Logic Design: ECE150: Prof. Risbud Prof.Union for the AdvancementHARDWARE DESIGN DESIGN Digital Logic Design: Advancement of Digital Logic Design:The Cooper Risbud ECE150: The Cooper Union for the ECE150: Prof. Risbud Science and Art HARDWARE DESIGN ASSIGNMENT #1 ASSIGNMENT #1 Fall 2007 Fall 2007 ASSIGNMENT #1 HARDWARE of Science and Art ...
View Full Document

This note was uploaded on 02/27/2012 for the course CHEMISTRY/ CH/ECE/PH/ taught by Professor Faculty during the Spring '08 term at Cooper Union.

Ask a homework question - tutors are online